Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-11-16
2002-03-26
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S063000, C365S210130
Reexamination Certificate
active
06363027
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device so designed as to decrease power consumed at the time of reading data from memory cells.
2. Description of the Related Art
In general, each transistor in a semiconductor memory device such as a ROM (Read Only Memory) can store binary information, such as “0” or “1”, or multi-value information which is expressed by the level of the gate voltage for turning on or off the transistor by controlling the threshold value.
The semiconductor memory device has transistors for a plurality of memory cells formed in rows and columns on a semiconductor substrate. The transistors for memory cells have gates connected to word lines formed in the row direction and drains connected to bit lines formed in the column direction.
In reading data stored in the memory cells in this semiconductor memory device, a memory cell corresponding to an input address signal is selected by a word line and a bit line which are enabled by a decoder. As the amount of the current that flows in the transistor of the selected memory cell is compared with the amount of the current that flows in a reference memory cell, data stored in the memory cell corresponding to the input address signal is read out.
In the aforementioned semiconductor memory device, each of the transistors for memory cells (hereinafter simply referred to as “memory-cell transistors”) is formed on the semiconductor substrate independently of other memory-cell transistors by a device isolation film. The drains of memory-cell transistors are connected to the associated bit lines and the sources are grounded.
While a circuit in the aforementioned semiconductor memory device, which is necessary for data reading, takes a simple structure, however, a contact for connecting a diffusion layer which forms the drain of each memory-cell transistor and the associated bit line should be formed on that diffusion layer. To form the contact in the diffusion layer of the drain, therefore, another contact should be formed, thus requiring a larger area for the diffusion layer than actually needed as a constituting element of the transistor. In other words, the structure of those memory-cell transistors stands in the way of increasing the integration level of memory cells.
As a solution to the aforementioned shortcoming of the memory-cell transistors, a virtual ground type structure and layout have been employed for memory-cell transistors in order to improve the integration level of memory cells.
Specifically, the drains and sources of memory-cell transistors adjoining in the row direction are formed by a common diffusion layer and a plurality of diffusion layers are connected in the column direction (by sub bit lines and sub virtual ground lines) so that the diffusion layers are connected in a matrix form. This makes it unnecessary to provide a contact in an area where each memory cell is to be formed. This structure can improve the integration level of memory-cell transistors as compared with the structure that needs such a contact.
To increase the reading speed of this virtual ground type semiconductor memory circuit, burst reading is carried out to read out stored data. At this time, the reading speed is improved by continuously reading multiple bits by single address setting.
Depending on the structure of a circuit in which a semiconductor memory circuit is used, however, the number of burst bytes (bits) to be read out by single address setting may vary. In this respect, a semiconductor memory circuit is so constructed as to be able to select plural types of bit quantities in burst reading.
A conventional semiconductor memory device which employs the aforementioned virtual ground type transistor structure for memory cells will now be described with reference to
FIGS. 1 and 2
.
FIGS. 1 and 2
are block diagrams showing the structure of the aforementioned virtual ground type semiconductor memory device. In this example, the number of burst reading bits selectable is either 4 bits or 8 bits.
In
FIGS. 1 and 2
, data is stored in memory-cell transistors which constitute each of 16 cell plates (memory cell plates
16
A
0
to
16
A
15
) of a memory cell area
16
A. Each cell plate is separated into two areas corresponding to two output terminals; for example, the cell plate
16
A
0
is separated into two areas corresponding to an output terminal TO
0
and an output terminal TO
1
.
That is, the cell plate
16
A
0
is separated into cell areas that store data to be respectively output from the output terminals TO
0
and TO
1
. Likewise, the cell plate
16
A
1
is separated into cell areas that store data to be respectively output from output terminals TO
2
and TO
3
. Likewise, each of the remaining cell plates
16
A
2
to
16
A
15
is separated into cell areas corresponding to output terminals TO
4
and TO
5
, or output terminals TO
30
and TO
31
.
In reading data from the aforementioned cell area of the semiconductor memory device, switching the burst output between 8 bits and 4 bits is determined how deep the cache or buffer is provided in the circuit that uses this semiconductor memory device. This bit switching is set by a control signal CSB, control signal RASB, control signal CASB and an address signal AD
0
when the semiconductor memory device is used. The following will discuss this bit switching step by step.
A control signal buffer
29
shapes the waveform of an input clock enable signal CKE and changes the voltage level thereof, and outputs the resultant signal as a control signal CK to a clock control circuit
30
. Likewise, the control signal buffer
29
shapes the waveform of an input clock signal CLK and changes the voltage level thereof, and outputs the resultant signal as a clock signal CL to the clock control circuit
30
.
The clock control circuit
30
sends the input control clock signal CL to a counter
18
when the input control signal CK has an “H” level and does not send the input clock signal CL to the counter
18
when the input control signal CK has an “L” level.
Further, the control signal buffer
129
shapes the waveform of the input control signal CSB and changes the voltage level thereof, and outputs the resultant signal as a control signal CSBI to an instruction decoder
28
. Likewise, the control signal buffer
29
shapes the waveform of the input clock signal RASB and changes the voltage level thereof, shapes the waveform of the input control signal CASB and changes the voltage level thereof, shapes the waveform of the input control signal MRB and changes the voltage level thereof, and outputs the resultant signals as control signals RASBI, CASBI and MRBI to the instruction decoder
28
, respectively.
The instruction decoder
28
sends a control signal MRSB
2
as an L-level signal to a switch circuit
14
when the control signals CSBI, RASBI, CASBI and MRBI all become an “L” level.
The switch circuit
14
sets the number of burst output bits (per one output terminal) based on the address signal AD
0
and an address signal AD
1
when the control signal MRSB
2
input has an “L” level.
Specifically, in the case where the control signal MRSB
2
input has an “L” level, the switch circuit
14
outputs a control signal MDBL
8
with an “H” level to set the number of burst output bits to 8 bits when the address signal AD
0
has an “L” level and the address signal AD
1
has an “H” level, and outputs the control signal MDBL
8
with an “L” level to set the number of burst output bits to 4 bits when the address signal AD
0
has an “H” level and the address signal AD
1
has an “L” level. Accordingly, the switch circuit
14
sets the number of bits sequentially output from each output terminal in the burst reading.
To specify memory-cell transistors in each of the cell plates
16
A
0
to
16
A
15
in the memory cell area
16
A and read data stored in those memory-cell transistors from output terminals TO
0
to TO
31
, for example, addresses AD
0
to AD
12
are input from an external CPU (Central Processing Unit) or the like.
Address
Dinh Son T.
NEC Corporation
LandOfFree
Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2816652