Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2008-04-01

2008-04-01

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S182000, C365S182000

Reexamination Certificate

active

07352642

ABSTRACT:
A semiconductor memory device includes a memory cell including a floating body region and storing data on the basis of the amount of charges in the floating body region; word lines; a counter cell array including counter cells provided to correspond to the word lines, the counter cell array storing the number of times of activation of the word lines; an adder incrementing the number of times of activation, the number of times of activation being read from the counter cell array; a counter buffer circuit temporarily storing the number of times of activation and writing back the incremented number of times of activation to the counter cell array; and a refresh request circuit outputting an instruction to execute a refresh operation to the memory cells connected to the word line when the number of times of activation reaches a predetermined value.

REFERENCES:
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patent: 6965526 (2005-11-01), Cavaleri et al.
patent: 2005/0185497 (2005-08-01), Ikeda et al.
patent: 2005/0195680 (2005-09-01), Higashi et al.
patent: 2007/0070745 (2007-03-01), Versen et al.
S. Okhonin, et al., “Principles of Transient Charge Pumping on Partially Depleted SOI Mosfets”, IEEE Electron Device Letters, vol. 23, No. 5, May 2002, pp. 279-281.
U.S. Appl. No. 11/331,169, filed Jan. 13, 2006, Ohsawa.
U.S. Appl. No. 11/539,447, filed Oct. 6, 2006, Ohsawa.

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