Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2011-03-15

2011-03-15

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S051000, C365S063000, C365S189170

Reexamination Certificate

active

07907439

ABSTRACT:
A semiconductor memory device comprises a plurality of cell arrays, each cell array containing a plurality of word lines, a plurality of bit lines crossing the word lines, and memory cells connected at intersections of the word lines and bit lines, the cell arrays arranged along the bit line; a plurality of bit line gates provided between the cell arrays and each operative to establish a connection between the bit lines in adjacent cell arrays; and a controlling circuit operative to form a data transfer path via the connection between the bit lines formed through the bit line gate when the controlling circuit accesses to the memory cell.

REFERENCES:
patent: 6335896 (2002-01-01), Wahlstrom
patent: 6483765 (2002-11-01), Han
John Wuu, et al., “The Asynchronous 24MB On-Chip Level-3 Cache for a Dual-Core Itanium® -Family Processor”, IEEE International Solid-State Circuits Conference, 2005, pp. 488-489 and 618.

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