Semiconductor memory device

Static information storage and retrieval – Systems using particular element – Ferroelectric

Reexamination Certificate

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C365S065000, C257SE21664

Reexamination Certificate

active

07872899

ABSTRACT:
The memory cell array includes a memory cell, the memory cell including a ferroelectric capacitor and a transistor. The memory cell array includes a word line selecting the memory cell, a plate line applying a drive voltage to the ferroelectric capacitor, and a bit line reading data from the ferroelectric capacitor. A selection transistor selectively connects the memory cell to the bit line. A dummy cell provides a reference potential, the reference potential being referred to for a potential read from the memory cell. A sense amplifier circuit includes a plurality of amplification circuits amplifying the potential difference between a bit-line pair. A decoupling circuit electrically cuts off the bit line between the amplification circuits.

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patent: 2005-175311 (2005-06-01), None

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