Semiconductor memory device

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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C365S154000, C365S189140, C365S203000

Reexamination Certificate

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07929333

ABSTRACT:
A semiconductor memory device includes a sub array including a plurality of memory cells each holding data arranged therein; a memory cell array including a plurality of the sub arrays arranged therein; paired bit lines including a first bit line and a second bit line connected to each of the sub arrays; and a write/read circuit arranged to correspond to each of the sub arrays, writing data to the sub array, and reading data from the sub array, wherein a pair of the sub array and the write/read circuit is repeatedly arranged along the paired bit lines, allowing the data to be transferred via the write/read circuit and the paired bit lines.

REFERENCES:
patent: 6023428 (2000-02-01), Tran
patent: 6515894 (2003-02-01), Osada et al.
patent: 7193912 (2007-03-01), Obara et al.
patent: 2003/0210565 (2003-11-01), Adams et al.
patent: 59-165292 (1984-09-01), None
U.S. Appl. No. 12/207,949, filed Sep. 10, 2008, Kawasumi, et al.

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