Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2011-01-04

2011-01-04

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S230080, C365S189050, C365S210100

Reexamination Certificate

active

07864618

ABSTRACT:
A semiconductor memory device includes a plurality of banks, each of which is constituted of a plurality of memory cell arrays that are aligned in series in the longitudinal direction, wherein each memory cell array includes a plurality of memory cells, and wherein memory cell arrays of banks are collectively aggregated into a plurality of blocks, each of which includes memory cell arrays aligned in the perpendicular direction, in connection with a plurality of DQ pads. DQ pads are arranged in proximity to blocks. Substantially the same distance is set between memory cells and DQ pads so as to reduce dispersions in access times with respect to all DQ pads, thus achieving high-speed access in the semiconductor memory device. The wiring region of IO lines is reduced in the center area of the chip.

REFERENCES:
patent: 5586078 (1996-12-01), Takase et al.
patent: 6041013 (2000-03-01), Kohno
patent: 6169699 (2001-01-01), Muraoka
patent: 6317377 (2001-11-01), Kobayashi
patent: 2003/0123320 (2003-07-01), Wright et al.
patent: 08-139287 (1996-05-01), None

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