Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2011-03-08

2011-03-08

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S158000

Reexamination Certificate

active

07903446

ABSTRACT:
A memory includes ferroelectric capacitors; cell transistors each including a drain connected to one electrode of each ferroelectric capacitor, and a gate connected to the word line; and memory cell blocks each including a reset transistor, a block selection transistor, and memory cells including the ferroelectric capacitors and the cell transistors, wherein sources of the cell transistors are connected to the plate lines, the other electrode of the ferroelectric capacitor is connected to one of the sub-bit lines, a source and a drain of the block selection transistor are connected to one of the sub-bit lines and one of the bit lines, a source of the reset transistor is connected to one of the plate lines or a fixed potential, and a drain of the reset transistor in each memory cell block is connected to one of the sub-bit lines, and the memory cell blocks configure a memory cell array.

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Masao Taguchi, et al., “A Capacitance-Coupled Bit Line Cell”, IEEE Transactions on Electron Devices, vol. ED-32, No. 2, Feb. 1985, pp. 290-295.

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