Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Differential sensing

Reexamination Certificate

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C365S185200

Reexamination Certificate

active

07864614

ABSTRACT:
A semiconductor memory device includes a memory cell array which includes a plurality of memory cells which are arrayed in a matrix at intersections between a plurality of word lines and a plurality of bit lines and a power supply circuit which includes a first band gap reference circuit which outputs a first output voltage, and a second band gap reference circuit which outputs a second output voltage having lower temperature characteristics than the first output voltage on a low temperature side, and generates a power supply voltage on the basis of the second output voltage at a time of a data write operation of the memory cells.

REFERENCES:
patent: 6147908 (2000-11-01), Abugharbieh et al.
patent: 6349060 (2002-02-01), Ogura
patent: 6667904 (2003-12-01), Takeuchi et al.
patent: 6906956 (2005-06-01), Marotta et al.
patent: 7692418 (2010-04-01), Jeong
patent: 2002-170391 (2002-06-01), None
patent: 2006-65945 (2006-03-01), None
patent: 2008-83825 (2008-04-01), None

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