Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2011-04-12

2011-04-12

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including signal clamping

C365S185170, C365S185050, C365S185210, C365S185250

Reexamination Certificate

active

07924632

ABSTRACT:
A semiconductor memory device comprising: a memory cell array having a plurality of memory cells that are arranged in a shape of a matrix along a plurality of bit lines arranged in parallel and a plurality of word lines intersecting orthogonally to the bit lines, and that have their data read out to the bit lines; a sense amplifier which detects a voltage or a current of the bit line, and which decides the read data from each of the memory cells; a clamping transistor which is connected between the sense amplifier and the bit lines, and which determines a voltage in a charging mode of the bit lines by a clamp voltage applied to a gate thereof; and a clamp voltage generation circuit which generates the clamp voltage so as to become larger as a distance from the sense amplifier to a selected one of the memory cells is longer.

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