Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2011-05-10
2011-05-10
Torres, Joseph D (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S782000, C714S784000, C714S785000
Reexamination Certificate
active
07941733
ABSTRACT:
A memory device includes an error detection and correction system with an error correcting code over GF(2n) wherein the system has an operation circuit configured to execute addition/subtraction with modulo 2n−1, and wherein the operation circuit has a first operation part for performing addition/subtraction with modulo M and a second operation part for performing addition/subtraction with modulo N (where, M and N are integers which are prime with each other as being obtained by factorizing 2n−1), and wherein the first and second operation parts perform addition/subtraction in parallel to output an operation result of the addition/subtraction with modulo 2n−1.
REFERENCES:
patent: 3668631 (1972-06-01), Griffith et al.
patent: 3668632 (1972-06-01), Oldham, III
patent: 4413339 (1983-11-01), Riggle et al.
patent: 4597083 (1986-06-01), Stenerson
patent: 4618955 (1986-10-01), Sharpe et al.
patent: 4709345 (1987-11-01), Vu
patent: 4796260 (1989-01-01), Schilling et al.
patent: 4849975 (1989-07-01), Patel
patent: 4910511 (1990-03-01), Nagata et al.
patent: 5031181 (1991-07-01), Sako et al.
patent: 5208815 (1993-05-01), Kojima
patent: 5459740 (1995-10-01), Glaise
patent: 5459742 (1995-10-01), Cassidy et al.
patent: 5561686 (1996-10-01), Kobayashi et al.
patent: 5754753 (1998-05-01), Smelser
patent: 5978953 (1999-11-01), Olarig
patent: 5995559 (1999-11-01), Hedberg
patent: 6185134 (2001-02-01), Tanaka
patent: 6256762 (2001-07-01), Beppu
patent: 6457156 (2002-09-01), Stenfort
patent: 6532565 (2003-03-01), Roth et al.
patent: 6581178 (2003-06-01), Kondo
patent: 6611938 (2003-08-01), Tanaka et al.
patent: 6651212 (2003-11-01), Katayama et al.
patent: 6757862 (2004-06-01), Marianetti, II
patent: 6769087 (2004-07-01), Moro et al.
patent: 7076722 (2006-07-01), Shibata
patent: 7096313 (2006-08-01), Chang et al.
patent: 7644342 (2010-01-01), Shibata
patent: 7650557 (2010-01-01), Totolos, Jr.
patent: 2004/0083334 (2004-04-01), Chang et al.
patent: 2006/0005109 (2006-01-01), Marelli et al.
patent: 2007/0019467 (2007-01-01), Toda
patent: 2007/0198902 (2007-08-01), Toda
patent: 2007/0220400 (2007-09-01), Toda et al.
patent: 2007/0266291 (2007-11-01), Toda et al.
patent: 2008/0082901 (2008-04-01), Toda
patent: 2010/0115383 (2010-05-01), Toda
patent: 2004-152300 (2004-05-01), None
U.S. Appl. No. 11/845,999, filed Aug. 28, 2007, Toda.
Kabushiki Kaisha Toshiba
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
Torres Joseph D
LandOfFree
Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2703018