Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Differential sensing

Reexamination Certificate

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C365S233100

Reexamination Certificate

active

07990791

ABSTRACT:
A memory includes a cell array; bit lines; word lines; sense amplifiers; first determination transistors receiving information data and making a connection between a first voltage source and a first determination node be in a conductive or a non-conductive state based on a logic value of the information data; second determination transistors receiving the information data detected by the sense amplifiers and making a connection between the first voltage source and a second determination node be in a conductive or a non-conductive state based on the logic value of the information data; a second voltage source charging the first and the second determination nodes; and a determination unit detecting potentials of the first determination node and the second determination node when a logic of the information data is inverted logically to determine maximum and minimum values of potential of the information data.

REFERENCES:
patent: 5657269 (1997-08-01), Nanamiya
patent: 5761125 (1998-06-01), Himeno
patent: 5903492 (1999-05-01), Takashima
patent: 6026034 (2000-02-01), Suzuki et al.
patent: 6418057 (2002-07-01), Hosogane
patent: 2000-173300 (2000-06-01), None

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