Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2011-07-12

2011-07-12

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S733000, C714S738000

Reexamination Certificate

active

07979758

ABSTRACT:
Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.

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