Semiconductor memory device

Static information storage and retrieval – Systems using particular element – Resistive

Reexamination Certificate

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C365S189110, C365S203000

Reexamination Certificate

active

07990753

ABSTRACT:
A nonvolatile semiconductor memory device having a plurality of unit cell arrays having memory cells each containing a first wiring and a second wiring intersecting each other, and a variable resistive element arranged at each intersection of said first wiring and said second wiring and electrically rewritable to nonvolatilely store a resistance value as data, characterized by comprising: a control circuit for applying a predetermined voltage to said memory cell in selectively accessing said memory cell; wherein said control circuit accumulates a predetermined electric charge in a parasitic capacitance of said memory cell included in a first unit cell array that is said specific unit cell array and not accessed at the first time, while on the other hand, accumulates a predetermined electric charge in a parasitic capacitance of said memory cell included in a second unit cell array that is said specific unit cell array other than said first unit cell array and not accessed at the second time after the passage of a predetermined time from said first time.

REFERENCES:
patent: 4800530 (1989-01-01), Itoh et al.
patent: 2007/0195582 (2007-08-01), Sakata et al.
patent: 2009/0262568 (2009-10-01), Ono et al.

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