Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-04-11

2001-11-13

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Parallel read/write

C365S051000, C365S063000

Reexamination Certificate

active

06317377

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, relates to a semiconductor memory device which is capable of exchanging data in a serial fashion between the device and the exterior while internally exchanging data with memory cells in a parallel manner, in order to realize high speed operations.
This application is based on Japanese patent application No. Hei 11-104623, the content of which is incorporated herein by reference.
2. Description of Related Art
In recent years, in concert with the dramatic advances in the performance of memory devices which have a large capacity and which are moreover capable of high speed operation. Examples of semiconductor memory devices having satisfactorily large capacity include, for example, DRAM (dynamic random access memory). DRAM conducts reading and writing of data by charging and discharging capacities within memory cells, so that it is impossible to force the operations within DRAM to follow at the speeds of system buses or microprocessors, which operate in accordance with high speed clock signals of a few hundred MHz or more. For this reason, structures have recently come to be adopted for DRAM in which the entirety of a memory cell array is divided into a plurality of banks which are mutually independent memory units, and access is conducted in order to differing banks while operating these banks in parallel. By doing this, it is possible to lower the internal DRAM data writing with respect to the external data writing while maintaining, from the point of view of the exterior of the DRAM, the appearance of data writing which matches the operational speed of the microprocessor.
In addition, strategies have been applied to lower the data writing within the DRAM with respect to the external data writing by sending and receiving data in a serial manner when data is exchanged between the DRAM and the exterior, while conducting data reading and writing among memory cell arrays within the DRAM in a parallel manner. The reason for this is that when data are selected within the memory cell arrays, it becomes difficult to conduct the adjustment of the timing between bits. For this reason, when data readout is conducted from a DRAM, parallel data comprising a plurality of bits are simultaneously read out from the memory cell arrays, these are converted to serial data, and are sequentially outputted to the exterior.
For example, by exchanging the 8-bit parallel data used internally with the exterior of the DRAM one bit at a time in a serial fashion, it is possible to reduce the data writing within the DRAM to ⅛ that in the exterior of the DRAM. Accordingly, in a DRAM with such a structure, a serial to parallel converter circuit and a parallel to serial converter circuit, are provided in order to interconvert the serial data which are exchanged with the exterior and the parallel data which are internally processed. Hereinbelow, the serial to parallel conversion will referred to as the serial-parallel conversion, and the parallel to serial conversion will be referred to as the parallel-serial conversion.
The structure of a semiconductor memory circuit such as that described above is shown in the block diagram of FIG.
13
. In order to facilitate the explanation, this diagram shows, in an overlapping fashion, the structure of a semiconductor memory device containing four memory cell arrays
1
-
1
through
1
-
4
, which has a 128 megabit capacity, and the structure of a semiconductor memory device containing eight memory cell arrays
1
-
1
through
1
-
8
, which has a capacity of 256 megabits. Accordingly, the memory cell arrays
1
-
5
through
1
-
8
and the serial-parallel/parallel-serial conversion circuits
3
-
5
through
3
-
8
(described hereinafter) are not present in the 128 megabit semiconductor memory device. The structure of the 128 megabit device is that which is conventionally employed, and the structure of the 256 megabit device simply represents an increase in capacity over that of the 128 megabit device.
In the figure, interface logic
2
includes, in addition to an input/output (I/O) interface circuit which serves to conduct data transfer between the semiconductor memory devices depicted in the figure and the exterior, a booster circuit which is provided with common DRAM, a fuse for redundancy, a substrate generating circuit, and the like. Furthermore, serial-parallel/parallel-serial conversion circuits
3
-
1
through
3
-
8
, which have the same structure, are provided between each memory cell array
1
-
1
through
1
-
8
and interface logic
2
, respectively, as circuits which correspond to the serial-parallel conversion circuit and the parallel-serial conversion circuit described above. For example the serial-parallel/parallel-serial conversion circuit
3
-
1
conducts readout and writing using parallel data with respect to the corresponding memory cell array
1
-
1
, and conducts the exchange of serial data with the exterior via interface logic
2
.
That is to say, serial-parallel/parallel-serial conversion circuit
3
-
1
has the function of converting parallel data successively read out from memory cell array
1
-
1
to serial data and outputting these to interface logic
2
, and has the function of converting serial data supplied from interface logic
2
to parallel data and writing these simultaneously into memory cell array
1
-
1
. Examples of semiconductor memory devices which are provided with such serial-parallel/parallel-serial conversion circuits include, for example, cache memories and field memories, which are memories for image processing which have a FIFO (first in first out) function, as well as video RAM which stores the data of displayed images.
Here,
FIG. 14
shows the connection relationships between the serial-parallel/parallel-serial conversion circuits
3
-
5
and
3
-
1
depicted in FIG.
13
and the input and output interface circuit
5
-
1
which is within the interface logic
2
depicted in Figure
13
. Here, the depiction centers on the data flow, and the concrete structure of the serial-parallel/parallel-serial conversion circuits is not depicted. In the Figure, the DQ
0
serial through DQ
7
serial are groups of 8 bit data which are inputted and outputted simultaneously between the semiconductor memory device and the exterior via the input and output interface circuit
5
-
1
. As will be shown hereinafter in the embodiments of the present invention, the writing and reading of the DQ
0
serial through DQ
7
serial depicted in
FIG. 14
are separate; however, so as to avoid complexity, the reading and writing functions are depicted together in a single signal line.
Furthermore, the DQ
0
parallel through DQ
3
parallel are eight-bit four-group data which are simultaneously inputted and outputted with the memory cell array
1
-
5
depicted in FIG.
13
. In the same way, the DQ
4
parallel through DQ
7
parallel are eight-bit four-group data which are simultaneously inputted and outputted with the memory cell array
1
-
1
depicted in FIG.
13
. Next, references
4
-
0
through
4
-
7
indicate shift registers which conduct the shift operation in a synchronous manner with the clock signal CLOCK; these all have the same structure. Furthermore, the data load signal LOAD serves to indicate the timing for the loading of data into these shift registers. The clock signal CLOCK and the data load signal LOAD are supplied to the shift registers described above at each stage; however, so as to avoid complexity, these connection relationships are not depicted. In
FIG. 14
, the DQ
0
serial through DQ
7
serial are depicted in such a way as to be connected to the bit
0
of the corresponding shift register; this indicates only that in the case of reading or writing with respect to the memory cell array, the 0th bit is initially processed, so that either the data of bit
0
are initially outputted from each shift register, or the data of bit
0
are initially applied to each register.
Shift registers
4
-
0
thro

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2602946