Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-03-28

2001-12-25

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230030

Reexamination Certificate

active

06333876

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device providing redundant remedy for a defective cell by use of fuse elements or the like
In general, in a semiconductor memory device having a plurality of memory cells arranged in an array on a semiconductor substrate made of silicon or the like, data read or write operation is performed in the following manner. A word line is selected by decoding an externally input row address signal, and a column line is selected by decoding an externally input column address signal. By the selected word line and column line, a memory cell is determined, and desired data is written on or read from the selected memory cell. The number of memory cells formed in an array is so enormous that a defective memory cell failing to operate normally may sometimes be included in the array of memory cells due to entering of a foreign substance in the fabrication process, generation of a defect in the substrate itself, or the like.
In consideration of the above situation, the design itself is made to provide redundant cells having the same function as the normal memory cells, together with a fuse circuit storing row address and column address information corresponding to a defective cell out of the plurality of memory cells. Once a defective cell is detected by probing or the like, a fuse element corresponding to the defective address is blown so as to replace the word line or column line corresponding to the defective cell with a spare (redundant) word line or column line. In this way, high yield is secured.
In a conventional dynamic redundancy circuit, determination on whether or not a redundancy circuit is used (redundancy determination) is necessary every active cycle. This lowers the operation speed. As one of circuitry techniques for solving this problem, provided is a shift redundancy circuit where a word line or column line corresponding to a defective cell is shifted to an adjacent word line or column line to effect redundant remedy.
Hereinbelow, a conventional semiconductor memory device having a shift redundancy circuit will be described with reference to FIG.
11
.
FIG. 11
schematically shows a conventional semiconductor memory device having a shift redundancy circuit. The conventional semiconductor memory device includes a memory cell array
101
having a plurality of memory cells arranged in an array and n+1 word lines (n is a positive integer) running across the memory cell array. The semiconductor memory device also includes a row decoder
102
placed on one of the sides of the memory cell array
101
where terminals of the word lines WL are located. The row decoder
102
decodes m row address signals AX (m is a positive integer) input thereto externally so as to select one of the n word lines.
The word line WL(n+1) is a spare (redundant) word line connected with a redundant cell section
101
a
in the memory cell array
101
.
A selector circuit
104
is placed between the memory cell array
101
and the row decoder
102
. The selector circuit
104
receives n output signals from the row decoder
102
and n defective cell designation signals SEL from a fuse circuit
103
, and switches the connection between output lines of the row decoder
102
and the word lines WL based on the defective cell designation signals SEL.
FIG. 12
shows the fuse circuit
103
and the selector circuit
104
in detail. As shown in
FIG. 12
, the fuse circuit
103
has a serial configuration of n serially connected fuse elements FS (FS(
1
) to FS(n)) that respectively correspond to the n decode output signals PX(
1
) to PX(n) output from the row decoder
102
shown in FIG.
11
. The terminal external of the first fuse element FS(
1
) in the serial configuration is connected with the power supply, and the terminal external of the n-th fuse element FS(n) in the serial configuration is grounded via a resistor R having a sufficiently large resistance value.
The selector circuit
104
includes n first switch circuits
104
a
and n second switch circuits
104
c
. The first switch circuits
104
a
open/close the connection between the output signals PX(n; n=1 to n) from the row decoder
102
and the corresponding word lines WL(n; n=1 to n) based on the defective cell designation signals SEL(n; n=1 to n). The second switch circuits
104
c
open/close the connection between the output signals PX(n; n=1 to n) from the row decoder
102
and the word lines WL(n+1; n=1 to n) adjacent to the corresponding word lines WL based on a signal inverted from the defective cell designation signal SEL(n; n=1 to n) by respective inverters
104
b.
The first switch circuits
104
a
and the second switch circuits
104
c
in n pairs have the same circuit configuration. For example, if the first switch circuit
104
a
is turned ON when the defective cell designation signal SEL is in the HIGH level, the second switch circuit
104
a
that receives the LOW-level defective cell designation signal SEL is turned OFF. This enables the output signal PX(n) from the row decoder
102
to be selectively output to either one of the adjacent word lines WL(n) and WL(n+1).
Hereinbelow, how to use and operate the fuse circuit
103
and the selector circuit
104
with the above configuration will be described.
For example, assume that no defective cell has been detected in the memory cell array
101
shown in FIG.
11
. In this case, no fuse element FS in the fuse circuit
103
is blown. Therefore, the potentials at all nodes SEL(n; n=1 to n) between the adjacent fuse elements FS are HIGH due to the high-resistance resistor-R. The potentials at the nodes SEL(n; n=1 to n) are input into the selector circuit
104
as the defective cell designation signals SEL(n; n=1 to n). This turns ON all the first switch circuits
104
a
so that the decode output signals PX(n; n=1 to n) are output to the corresponding word lines WL(n; n=1 to n).
Next, assume that any of the memory cells connected to the third word line WL(
3
) has been found defective. In this case, the third fuse element FS(
3
) is blown. Therefore, while the first defective cell designation signal SEL(
1
) and the second defective cell designation signal SEL(
2
) are kept in the HIGH level, the third to n-th defective cell designation signals SEL(
3
) to SEL(n) are turned to the LOW level. As a result, in the third circuit pair of the selector circuit
104
receiving the third output signal PX(
3
), while the first switch circuit
104
a
is turned OFF, the second switch circuit
104
c
is turned ON. This allows the third output signal PX(
3
) from the row decoder
102
to be output to the fourth word line WL(
4
). Likewise, the fourth to n-th output signals PX(
4
) to PX(n) from the row decoder
102
are output to the word lines WL downstream adjacent to the corresponding word lines WL. In other words, the word lines WL to which the output signals are output are shifted to those having a one-incremented numerical subscript.
In short, when a defective cell connected with the third word line WL(
3
) is to be remedied, the fuse element FS(
3
) corresponding to the third word line WL(
3
) is blown so that the connection between the third output signal PX(
3
) from the row decoder
102
and the third word line WL(
3
) is cut off. The connection of the third output signal PX(
3
) and the subsequent output signals with the word lines WL is then shifted by one in the order of the placement of the word lines WL. This remedy of a defective cell ensures high yield.
In addition, the defective cell designation signals SEL for determining the connection between the output signals PX from the row decoder
102
and the word lines WL are DC voltages that are determined right after powering based on the blown states of the fuse elements PS. This eliminates the necessity of performing the redundancy determination every active cycle as is required for the dynamic redundancy circuit, thereby realizing high-speed operation.
However, the above c

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