Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-05-25

2001-02-27

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185110, C365S230030, C365S230040

Reexamination Certificate

active

06195284

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and in particular to a semiconductor memory device having a multi-valued memory cell that stores a plurality of bits.
2. Description of the Prior Art
As means to realize a non-volatile semiconductor memory device, a technology using a multi-valued memory cell memorizing information with bits is known. In such a semiconductor memory device, threshold values for the multi-valued memory cell are set into multi-steps, and for example, when threshold values are set into four steps, four kinds of information, that is, 2-bit information will be stored in a single multi-valued memory cell.
Accordingly, a memory capacity of the same quantity as a normal semiconductor memory device, which can only store one-bit information, will become obtainable with a half cells of the above-described semiconductor memory device. Configuration and read-out of such a conventional semiconductor memory device will be described as follows with reference to drawings.
FIG. 6
is a block diagram showing a configuration of a conventional non-volatile semiconductor memory device. The semiconductor memory device in
FIG. 6
comprises a memory cell array in which multi-valued memory transistors are disposed configuring a matrix. This memory array is classified into a cell plate L and a cell plate R, and further the cell plate L is classified into a cell plate L
0
corresponding with an even address and a cell plate L
1
corresponding with an odd address while the cell plate R is classified into a cell plate R
0
corresponding to an even address and a cell plate R
1
corresponding with an odd address.
Memory cell transistors ML
0
, ML
1
, MR
0
, and MR
1
are respectively set at any one of threshold values among four kinds of threshold values VT
0
, VT
1
, VT
2
, and VT
3
(but, VT
0
<VT
1
<VT
2
<VT
3
). Accordingly, two-bit information will be stored at the memory cell transistors ML
0
, ML
1
, MR
0
, and MR
1
respectively.
A row decoder
12
selects respectively one among a plurality of word lines WL and among word lines WR in accordance with an address signal inputted from outside.
A column decoder
13
controls column selectors
14
L
0
,
14
L
1
,
14
R
0
, and
14
R
1
based on input address signals. A column selector
14
L
0
selects one among a plurality of bit line BL
0
, a column selector
14
L
1
selects one among a plurality of bit line BL
1
, a column selector
14
R
0
selects one among a plurality of bit line BR
0
, and a column selector
14
R
1
selects one among a plurality of bit line BR
1
.
Sense amplifiers
15
L
0
,
15
L
1
,
15
R
0
, and
15
R
1
amplify outputs from column selectors
14
L
0
,
14
L
1
,
14
R
0
, and
14
R
1
.
Here, the row decoder
12
applies three-stage word-line voltage as shown in
FIG. 7
to selected word-lines WL and WR in order to read out information of memory cell transistors ML
0
, ML
1
, MR
0
, and MR
1
. In
FIG. 7
, a mid-potential between the threshold values VT
0
and VT
1
is determined as a word
1
, a mid-potential between the threshold values VT
1
and VT
2
is determined as a word
2
, and a mid-potential between the threshold values VT
2
and VT
3
is determined as a word
3
.
This will serve to sequentially cause data D
1
corresponding with the potential of the word
1
, D
2
corresponding with the potential of the word
2
, and D
3
corresponding with the potential of the word
3
to appear at outputs of the sense amplifiers
15
L
0
,
15
L
1
,
15
R
0
, and
15
R
1
.
Latch circuits
16
L
0
a,
16
L
1
a,
16
R
0
a,
and
16
R
1
a
are circuits to maintain the data D
1
, latch circuits
16
L
0
b,
16
L
1
b,
16
R
0
b,
and
16
R
1
b
are circuits to maintain the data D
2
, latch circuits
16
L
0
c,
16
L
1
c,
16
R
0
c,
and
16
R
1
c
are circuits to maintain the data D
3
.
A binary conversion circuit
17
L
0
implements exclusive OR operation on the output data D
3
of output data D
1
of the latch circuit
16
L
0
a
and output data D
3
of the latch circuit
16
L
0
c,
outputs its result as high order data HL
0
, and outputs output data D
2
of the latch circuit
16
L
0
b
as low order data LL
0
.
A binary conversion circuit
17
L
1
implements exclusive OR operation on the output data D
3
of output data D
1
of the latch circuit
16
L
1
a
and output data D
3
of the latch circuit
16
L
1
c,
outputs its result as high order data HL
1
and outputs output data D
2
of the latch circuit
16
L
1
b
as low order data LL
1
.
The binary conversion circuit
17
R
0
implements exclusive OR operation on the output data D
1
of the latch circuit
16
R
0
a
and output data D
3
of the latch circuit
16
R
0
c,
outputs its result as high order data HR
0
and outputs output data D
2
of the latch circuit
16
R
0
b
as low order data LR
0
.
In addition, the binary conversion circuit
17
R
1
implements exclusive OR operation on the output data D
1
of the latch circuit
16
R
1
a
and output data D
3
of the latch circuit
16
R
1
c,
outputs its result as high order data HR
1
and outputs output data D
2
of the latch circuit
16
R
1
b
as low order data LR
1
.
The output data conversion circuits
18
L and
18
R select either one of input data in accordance with an input address signal so as to output it as output data OUTL and OUTR.
A conventional semiconductor memory device having a multi-valued memory cell applies word-line voltage as in
FIG. 7
to a memory cell transistor selected with the row decoder
12
, the column decoder
13
and the column selectors
14
L
0
,
14
L
1
,
14
R
0
, and
14
R
1
so as to read out data D
1
to D
3
sequentially and output high order data or low order data out of obtained two bits. That is, regardless whether the high order data or the low order data are read out, the order of variation of word-line voltage always remains same. Therefore, when high order data are appointed to be read out, unnecessary data D
2
will be read out while unnecessary data D
1
and D
3
will be read out when low order data are appointed to be read out.
As described above, the conventional semiconductor memory device having a multi-valued memory cell, which varies the word-line voltage into multiple stages, has a problem that it requires longer read-out time than semiconductor memory device which is not a multi-valued one.
BRIEF SUMMARY OF THE INVENTION
Object of the Invention
Object of the present invention is to shorten read-out time in a semiconductor memory device having a multi-valued memory cell memorizing a plurality of bit.
Summary of the Invention
A semiconductor memory device of the present invention comprises a memory array in which multi-valued memory cells (ML
0
, ML
1
, MR
0
, and MR
1
) which store a plurality of bits are disposed in a matrix, a plurality of word lines (WL and WR) provided in memory cells on each row, a plurality of bit lines (BL
0
, BL
1
, BR
0
, and BR
1
) provided in memory cells on each column, recognition means (
1
) to judge whether an input address signal designates upper data or designates lower data among a plurality of bits, row selection means (
2
) to select word lines in accordance with input address signals and apply only a smallest word line voltage necessary for reading out upper data or lower data among word line voltage with a plurality of levels to selected word lines, column selection means (
3
,
4
L
0
,
4
L
1
,
4
R
0
, and
4
R
1
) to select bit lines in accordance with input address signals, and output means (
6
L
0
a
to
6
L
0
C,
6
L
1
a
to
6
L
1
c,
6
R
0
a
to
6
R
0
c,
6
L
1
a
to
6
L
1
c,
7
L
0
,
7
L
1
,
7
R
0
,
7
R
1
,
8
L, and
8
R) generating output data in accordance with selected bit line levels.
Thus, in accordance with results of the address recognition means the row selecting means apply only the smallest word line voltage necessary for reading out upper data or lower data to the selected word lines so that unnecessary word line voltage will no longer be applied as in conventional cases.
In addition, a semiconductor memory device o

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