Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-11-15

2001-12-04

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100

Reexamination Certificate

active

06327210

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device like a dynamic random access memory (DRAM).
In a known semiconductor memory device, e.g., DRAM, in particular, data stored on its memory cell is usually lost due to its own physical properties after a certain period of time has passed. To avoid such an unfavorable situation, refreshing is needed. And to perform this refreshing a t regular intervals, a system utilizing a DRAM should control the refresh operation. Accordingly, a DRAM requiring refreshing is not so easy to handle as other semiconductor memory devices requiring no refreshing.
Hereinafter, a known semiconductor memory device will be described.
FIG. 25
is a block diagram illustrating a configuration for a main part of a known semiconductor memory device. As shown in
FIG. 25
, the memory device includes address buffer
3
, row decoder
4
, column decoder
5
, sense amplifier
6
, input/output buffer
7
, memory array
8
, refresh counter
9
and command decoder
10
. A set of addresses, consisting of row and column addresses, are externally input through the address buffer
3
and decoded by the row and column decoders
4
and
5
, respectively. It should be noted that these column and row addresses externally input will be herein called an “external address” collectively. The sense amplifier
6
is provided to amplify the data stored on a memory cell. The input/output buffer
7
is provided to input and output data therethrough. In the memory array
8
, a great number of memory cells, each requiring refreshing, are arranged in columns and rows. The refresh counter
9
is a collection of counters that are provided in such a number as needed to decode row addresses. The command decoder
10
decodes an externally input command to generate a refresh enable signal during refreshing. In response to the refresh enable signal, the refresh counter
9
counts the number of row addresses provided one by one.
The known semiconductor memory device with such a configuration performs refreshing responsive to a refresh command/REF that has been input to the device. On decoding the refresh command /REF, the command decoder
10
outputs the refresh enable signal to the refresh counter
9
. In response, the refresh counter
9
starts counting the pulses of the refresh enable signal to find associated row addresses internally. And memory cells, which have been selected by the row decoder
4
by reference to the row addresses, are refreshed as a result. This operation should be performed a predetermined number of times within a predefined refresh cycle.
In the known configuration, however, the system outside of the DRAM should include a refresh controller to meet the requirements of refreshing. In addition, while the DRAM is performing the refresh operation, the system controls accesses to the DRAM so that the DRAM cannot be externally accessed. For these reasons, the DRAM is not so easy to handle as other semiconductor memory devices requiring no refreshing.
To cope with such a problem, a DRAM, which looks like requiring no refreshing, was proposed as disclosed in Japanese Laid-Open Publication No. 9-190689, in which two transistors are provided for a single memory cell and one of these two transistors is exclusively used for refreshing. A DRAM, including memory cells with such a two-transistor, one-capacitor construction, needs a chip area twice larger than a DRAM, including memory cells with a normal one-transistor, one-capacitor construction, does. Nevertheless, a DRAM of the former type still operates at the same frequency as a DRAM of the latter type. Thus, this alternative construction is not advantageous in cost effectiveness.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor memory device that allows for high-speed random accesses and yet needs no external refreshing or no refresh controllers built in its external system.
To achieve this object, a semiconductor memory device according to the present invention is so constructed as to start refreshing automatically unless external commands are input to the device.
An inventive semiconductor memory device includes: an array of memory cells; command detecting means for detecting input or no input of an external command that requests access to one of the memory cells; and refreshing means for performing a refresh operation on associated one of the memory cells if the detecting means has detected no input of the command.
In one embodiment of the present invention, the refreshing means cancels the refresh operation when the detecting means detects the input of the command.
In another embodiment of the present invention, two transistors are connected to each said memory cell in the memory array.
In this particular embodiment, each of the two transistors in the memory cell is used for accessing and refreshing purposes.
In still another embodiment, the memory cell is accessed synchronously with an external clock signal, and the refreshing means performs the refresh operation synchronously with the external clock signal.
In this particular embodiment, if a frequency of the external clock signal is higher than a frequency corresponding to a refresh cycle time, the refreshing means performs the refresh operation synchronously with the external clock signal.
Alternatively, if a frequency of the external clock signal is equal to or lower than a frequency corresponding to a refresh cycle time, the refreshing means generates a refresh clock signal with a frequency higher than the frequency of the external clock signal and performs the refresh operation synchronously with a logical product of the refresh clock signal and the external clock signal.
As another alternative, if a frequency of the external clock signal is higher than a frequency corresponding to a refresh cycle time and if the command has not been input externally for a predetermined period of time or more, the refreshing means generates a refresh clock signal with a frequency lower than the frequency of the external clock signal and performs the refresh operation synchronously with a logical product of the refresh clock signal and the external clock signal.
In still another embodiment, two transistors are provided for each said memory cell in the memory array and two signal propagation paths are provided for the array. Each said line is provided with an address latch. The refreshing means includes a comparator for comparing a refresh address, which has been latched in one of the address latches during the refresh operation, to an external address, which was latched in the other address latch just before the refresh operation. If the refresh address matches to the external address, then the refreshing means cancels the refresh operation on one of the memory cells that is specified by the refresh address.
In yet another embodiment, the refreshing means includes: an address latch for latching an external address that is input externally during a normal operation in which one of the memory cells is accessed; and a comparator for comparing a refresh address, which has been input during the refresh operation, to the external address that was latched in the address latch just before the refresh operation. If the refresh address matches to the external address, then the refreshing means cancels the refresh operation on one of the memory cells that is specified by the refresh address.
In this particular embodiment, the device further includes at least one additional address latch and at least one additional comparator that perform the same functions as the address latch and the comparator, respectively. The refresh address is compared to the external address latched in each said address latch during the refresh operation.
In still another embodiment, if the refresh address matches to the external address latched in the address latch, the refreshing means updates the refresh address.
In yet another embodiment, the refreshing means includes a comparator for comparing an external address to a refres

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