Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-06-28

2001-09-04

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S149000

Reexamination Certificate

active

06285613

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-183914, filed Jun. 29, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and more specifically to a high-density, high-speed dynamic semiconductor memory device.
Conventional semiconductor memory devices include dynamic semiconductor memory devices (hereinafter referred to as DRAMs: Dynamic Random Access Memories) in which each memory cell is composed of one cell capacitor and one cell transistor. The DRAMs are adapted for high packing density because each memory cell takes up a small amount of area. In recent years, therefore, the development of products has been pushed forward in various places to increase the packing density and operating speed of the DRAMS.
In order to increase the packing density, it is required to reduce the thickness of the gate oxide film of each cell transistor and thereby scale down the dimensions of it. However, the thinner the gate oxide film, the lower the supply voltage to the memory cell array has to be set, since the withstand voltage is lowered. On the other hand, the lower the supply voltage to the memory cell array, the lower the signal level for sensing data stored in each memory cell becomes. As the supply voltage to the memory cell array is lowered, the threshold voltage V
thn
of the N-channel MOS transistors of each flip-flop (F/F) that discriminates a signal voltage in the initial stage of a sense operation has to be lowered. However, it is not easy to lower the threshold voltage V
thn
according to scaling rules.
The sense margin of sense amplifiers depends on the threshold voltage V
thn
. Thus, when the magnitude of the threshold voltage V
thn
is large and the signal level to be detected is low, the normal sense operation becomes difficult to perform. Difficulties are therefore involved in adopting conventional sense amplifiers.
The S/N ratio of the conventional sense amplifiers depends on the transition characteristic (driving speed K) of the common source voltage of N-channel MOS transistors in each F/F because of unbalance of electric parameters of a pair of bit lines and a sense amplifier. With the conventional sense amplifiers, therefore, the lower the driving speed K with which the precharged voltage discharges down to ground voltage, the higher the sensitivity becomes. Thus, the conventional sense amplifiers have a problem that, as semiconductor memory devices advance in fine device structure and speed, it becomes more and more difficult to sense the signal level of each memory cell.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a sense amplifier circuit which is easy to sense signal levels of memory cells and suitable for use with high-density high-speed DRAMS.
In a semiconductor memory device of the present invention, a sense amplifier connected to a pair of complementary bit lines has a CMOS flip-flop composed of N-channel MOS transistors (NMOS transistors) and P-channel MOS transistors (PMOS transistors) and first and second source capacitors are connected to the common sources of the NMOS transistors and the PMOS transistors, respectively, as auxiliary capacitors for a cell capacitor. Each of the source capacitors is a trench or stacked capacitor of three-dimensional structure.
Specifically, a semiconductor memory device of the invention comprises: a memory cell array; a sense amplifier connected to a pair of complementary bit lines, the sense amplifier having a CMOS flip-flop circuit composed of a pair of PMOS transistors having their sources connected together and a pair of NMOS transistors having their sources connected together; a first source capacitor connected to the common sources of the pair of PMOS transistors; and a second source capacitor connected to the common sources of the pair of NMOS transistors.
Preferably, each of the first and second source capacitors consists of a trench capacitor or stacked capacitor formed between the corresponding transistors.
Preferably, the sense amplifier is connected between first and second supply voltages, the first source capacitor stores an amount of charge corresponding to the sum of the average value of the first and second supply voltages and the absolute value of the threshold voltage of the PMOS transistors, the second source capacitor stores an amount of charge corresponding to the sum of the average value of the first and second supply voltages and the absolute value of the threshold voltage of the NMOS transistors, and in a state where the sense amplifier is coupled with a cell capacitor in the memory cell array a sense operation is performed which divides charges stored on the first and second source capacitors between the capacitance associated with the bit lines and the capacitance of the cell capacitor.
Preferably, the sense amplifier is connected between first and second supply voltages, the CMOS flip-flop circuit comprises a first CMOS inverter consisting of one of the PMOS transistors and one of the NMOS transistors and a second CMOS inverter consisting of the other of the PMOS transistors and the other of the NMOS transistors, and a restore operation for a cell capacitor is performed by connecting the first supply voltage to one of the bit lines through a switching transistor connected to the first supply voltage and the PMOS transistor in the first CMOS inverter and connecting the second supply voltage to the other of the bit lines through a switching transistor connected to the second supply voltage and the NMOS transistor in the second CMOS inverter.
Preferably, a precharge operation for the bit lines is performed by discharging charges stored on the first and second source capacitors through the NMOS and PMOS transistors in the first CMOS inverter, one of the bit lines which is connected to the common drains of the NMOS and PMOS transistors in the first CMOS inverter and a switching transistor connected to the one of the bit lines to a terminal placed at the average voltage of the first and second supply voltages and discharging the charges stored on the first and second source capacitors through the NMOS and PMOS transistors in the second CMOS inverter, the other of the bit lines which is connected to the common drains of the NMOS and PMOS transistors in the second CMOS inverter and a switching transistor connected to the other of the bit lines to a terminal placed at the average voltage of the first and second supply voltages.
Another semiconductor memory device of the present invention comprises: a memory cell array having memory cells arranged in rows and columns, each of the memory cells being composed of one cell transistor and one cell capacitor; word lines each extending in the row direction of the memory cell array and pairs of complementary bit lines each extending in the column direction of the memory cell array; and sense amplifiers each connected with a corresponding one of the pairs of complementary bit lines, in each of the memory cells the cell capacitor having its plate connected to the source of the cell transistor and the cell transistor having its gate connected with a corresponding one of the word lines and its drain connected to one bit line of a corresponding one of the pairs of complementary bit lines, each of the sense amplifiers comprising a CMOS flip-flop circuit composed of first and second PMOS transistors and first and second NMOS transistors, in the CMOS flip-flop circuit the first and second PMOS transistors having their sources connected to a first supply voltage through a first switching transistor and the first and second NMOS transistors having their sources connected to a second supply voltage through a second switching transistor, the first PMOS transistor and the first NMOS transistor having their drains connected together to the one bit line and their gates connected together to the other bit line of the cor

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