Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-02-17

2001-03-06

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S226000, C365S230060, C365S189110

Reexamination Certificate

active

06198671

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device including a dynamic random access memory (DRAM) and, more particularly, to a semiconductor memory device having a function of switching a low-level potential to be applied to memory cell arrays, bit lines, and sense amplifiers depending on internal operation of the memory.
In recent years, in an attempt of realizing higher integration and faster operation of semiconductor memory devices including DRAMs, further miniaturization of transistors and lowering of the operating supply voltage for the transistors have been pursued. In DRAMs, in general, as the operating supply voltage is lowered, the amount of charges accumulated in a memory cell capacitor decreases, degrading the charge retention property of the memory cell. As transistors are miniaturized, the breakdown voltage of a gate oxide film decreases. It is therefore difficult to maintain the reliability of memory cell transistors as long as a conventional method in which the read potential of a memory cell is secured by raising the potential at a word line is employed. In recent years, also, there have been brought to market a type of semiconductor devices, called custom LSIs, where large-capacity memories such as DRAMs and custom logics such as CPUs or ASICs are integrated on one chip. To meet these trends, demands for designs using no internal boosted potential and process simplification by such designs have increased.
However, in order to retain the read potential of a memory cell without boosting a word line at the same level as that obtained by boosting the word line, the threshold potential of the memory cell transistor must be lowered. Lowering the threshold potential increases a sub-threshold leak current of the memory cell transistor. This also results in degradation of the charge retention property. As one conventional method that solves the above problem, a so-called boosted sense ground (BSG) method disclosed in U.S. Pat. No. 5,687,123 is known.
The circuit configuration and operation in the conventional boosted sense ground method will be described with reference to relevant drawings.
FIG. 16
is a partial circuit diagram showing the connection between a memory cell in the inactivated state and an activated sense amplifier in a DRAM. Referring to
FIG. 16
, a memory cell
500
includes: a memory cell capacitor
501
; and a memory cell transistor
502
having a gate connected to a word line WL, a drain connected to a bit complementary line /BL, and a source connected to one electrode of the memory cell capacitor
501
. An internally generated cell plate potential VCP is applied to the other electrode of the memory cell capacitor
501
, and an internally generated substrate potential VBB is applied to the memory cell transistor
502
.
A sense amplifier
510
has a cross-coupled structure including: a first inverter
511
composed of a first n-type transistor
511
n
and a first p-type transistor
511
p
; and a second inverter
512
composed of a second n-type transistor
512
n
and a second p-type transistor
512
p
. One output of the structure, namely, the common drain of the first n-type transistor
511
n
and the first p-type transistor
511
p
is connected to the bit complementary line /BL, while the other output, namely, the common drain of the second n-type transistor
512
n
and the second p-type transistor
512
p
is connected to a bit line BL. The sources of the first n-type transistor
511
n
and the second n-type transistor
512
n
are connected to a sense amplifier (SA) ground potential line SAN, while the sources of the first p-type transistor
511
p
and the second p-type transistor
512
p
are connected to a sense amplifier (SA) supply potential line SAP.
FIG. 17
shows a circuit configuration in the boosted sense ground method. An internal circuit
550
of a DRAM includes sense amplifiers and memory cells. The line for the ground potential in the internal circuit
560
is connected to a BSG potential line
560
, which is connected with a BSG driver
570
. The BSG driver
570
includes: a first NMOS transistor
571
having a diode-connected gate and a grounded source; and a second NMOS transistor
572
having a gate receiving a control signal &phgr; and a grounded source. The two NOMS transistors have a common drain. The BSG potential line
560
is also connected with a BSG potential compensation circuit
580
that supplies a current to the BSG potential line
560
when the BSG potential falls below a predetermined value.
The operation of the above DRAM employing the boosted sense ground method is as follows.
FIGS.
18
(
a
) and
18
(
b
) show waveforms of the SA ground potential SAN and the SA supply potential SAP during read operation by a sense amplifier, observed when the boosted sense ground method is not employed and when it is employed, respectively. In FIGS.
18
(
a
) and
18
(
b
), times tc and td represent the drive timings of the word line WL and the sense amplifier, respectively.
As is observed from FIG.
18
(
b
), when the boosted sense ground method is employed, the ground potential for sense amplifiers, namely, the BSG potential is kept above the threshold voltage of the first NMOS transistor
571
of the BSG driver
570
shown in
FIG. 17
due to the clamping function of the transistor until time td at which the sense amplifier is activated.
At time td, the second NMOS transistor
572
shown in
FIG. 17
is turned ON in response to the control signal &phgr; and kept ON until time tn. This suppresses the BSG potential from rising due to a current flowing from the sense amplifier.
In the boosted sense ground method, therefore, the potential at the bit complementary line /BL, which is the one of the bit line pair having the lower potential, is higher than the ground potential VSS. This increases a first bias voltage VGS
1
, namely, a gate-drain voltage of the memory cell transistor
502
shown in
FIG. 16
, compared with the case shown in FIG.
18
(
a
) where the boosted sense ground method is not employed. As the value of the first bias voltage VGS
1
is greater, a sub-threshold leak current flowing toward the channel of the memory cell transistor
502
in the inactivated state becomes smaller exponentially. The sub-threshold leak current normally flows in such a direction that data retained in the memory cell capacitor
501
shown in
FIG. 16
may be destructed. However, by setting the BSG potential at a level higher than the ground potential VSS to secure a large value for the first bias voltage VGS
1
, such a sub-threshold leak current can be reduced. The reduction of the sub-threshold leak current contributes to improving the charge retention property of the DRAM.
However, the semiconductor memory device employing the conventional boosted sense ground method has the following problem. In this method, the SA ground potential SAN for the sense amplifier
510
shown in
FIG. 16
is kept higher than the ground potential VSS by the value of the threshold potential of the first NMOS transistor
571
shown in FIG.
17
. Accordingly, the value of a second bias voltage VGS
2
that is a source-gate voltage of the first n-type transistor
511
n
shown in
FIG. 16
is smaller than the case shown in FIG.
18
(
a
) where the SA ground potential SAN is not boosted.
The second bias voltage VGS
2
is a bias voltage from the source toward the gate of the first n-type transistor
511
n
of the sense amplifier
510
. If this voltage value is small, the first n-type transistor
511
n
degrades in its current drive ability and thus in its ability of approximating the bit complementary line /BL to the SA ground potential SAN. As a result, the speed at which a sufficient potential is generated between the bit line pair BL, /BL, called a sense speed, decreases.
The second bias voltage VGS
2
also decreases when the supply voltage is lowered to realize lowering of the operating voltage of DRAMs. Therefore, the problem of reduction in sense speed is specifically significant in DRAMs. If the supply voltage is extremel

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