Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2000-04-03
2001-07-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S189040, C365S230060
Reexamination Certificate
active
06262922
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor memory device. More specifically, the invention relates to a dynamic semiconductor memory device (DRAM) required to rewrite read data.
2. Related Background Art
A memory cell array of a DRAM is formed by providing bit lines and word lines, which intersect each other, and by arranging dynamic memory cells, each of which has one transistor/one capacitor, at the respective intersections. Each of the bit lines of the memory array is provided with a bit line sense amplifier. By selectively driving the word lines, data of a plurality of memory cells are read out to a plurality of corresponding bit lines. These bit line data are selected by a column selecting gate to be transferred to a corresponding data line. The data transferred to the data line are detected and amplified by a corresponding one of data line sense amplifiers to be outputted.
Thus, in the data readout operation for the DRAM, the bit line data are detected and amplified by the corresponding one of the bit line sense amplifiers having a small drive capacity. Therefore, after the potential amplitude of the bit lines increases to such an extent that data destruction does not occur, the column selecting gate is open, so that the bit line data are transmitted to the data line (step (a)). Because, if not so, there is the possibility that data destruction occurs due to charge distribution caused by connecting the bit lines to the corresponding data line. After the bit line data are transferred to the data line, the data line is separated from the corresponding one of the data line sense amplifiers, and the transferred data are amplified to a full amplification level to be outputted (step (b)). The reason why the data line is separated is that a data line capacity is separated from the corresponding one of the data line sense amplifiers to carry out rapid detection and amplification.
In the above described typical data readout method for DRAMs, there is a problem in order to further promote the capacity increase, scale down and accelerating of DRAMs. That is, with the capacity increase and scale down of DRAMs, a large number of memory cells are connected to bit lines, so that the bit line capacity increases. On the other hand, with the scale down, the drive capacity of the bit line sense amplifier, which must be arranged in a bit line pitch, relatively decreases. Therefore, it takes a lot of time to amplify data read out to the bit lines, to some extent of amplitude. This obstructs rapid readout.
Conventionally, as rapid data readout techniques for DRAMs, there are proposed (1) a system for providing a read-only sense amplifier and a restore-only sense amplifier in a bit line (Japanese Patent Laid-Open No. 8-147975), and (2) a system for providing a global bit line shared by a plurality of bit lines in a memory array, providing a pre-sense amplifier in each of the bit lines, and providing a restoring sense amplifier in the global bit line (Japanese Patent Laid-Open No. 5-144253).
However, in these systems, although the sense amplifiers are divided every function, all of the sense amplifiers must be arranged in a bit line pitch in a memory cell array region on a layout. As described above, in the memory array region, the bit line pitch is very small by the scale down technique, so that there is a limit to the drive capacity of the sense amplifier arranged in the memory cell array region.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a dynamic semiconductor memory device capable of carrying out rapid data readout.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor memory device comprises: a memory cell array including a plurality of bit lines, a plurality of word lines intersecting the bit lines, and a plurality of dynamic memory cells, each of said cells is arranged at a corresponding one of intersections between the bit lines and the word lines; a row decoder for selectively driving at least one of the word lines of said memory cell array; bit line sense amplifiers, which are connected to the bit lines of said memory cell array to be activated by a first sense amplifier activating signal for detecting and amplifying data read out to said plurality of bit lines, said data being read out responsive to the word line selectively driven by said row decorder; column selecting gates, which are selectively driven by a column selecting signal generated behind said first sense amplifier activating signal, for connecting selected said bit lines of said memory cell array to corresponding data lines; and a data line sense amplifier connected to said data lines to be activated by a second sense amplifier activating signal generated behind said column selecting signal, said data line sense amplifier being associated with said bit line sense amplifier for detecting and amplifying data read out to said bit lines and said data lines.
According to another aspect of the present invention, a semiconductor memory device comprises: a memory cell array including a plurality of bit lines, a plurality of word lines intersecting the bit lines, and a plurality of dynamic memory cells, each of said cells is arranged at a corresponding one of intersections between the bit lines and the word Lines; a row decoder for selectively driving at least one of the word lines of said memory cell array; bit line sense amplifiers, which are connected to the bit lines of said memory cell array to be activated by a first sense amplifier activating signal for detecting and amplifying data read out to said plurality of bit lines, said data being read out responsive to the word line selectively driven by said row decorder; column selecting gates, which are selectively driven by a column selecting signal generated behind said first sense amplifier activating signal, for connecting selected said bit lines of said memory cell array to corresponding data lines; and a data line sense amplifier connected to said data lines to be activated by a second sense amplifier activating signal generated behind said column selecting signal, said data line sense amplifier being associated with said bit line sense amplifier for detecting and amplifying data read out to said bit lines and said data lines, wherein data, which is selected by said column selecting signals, of data read out to said a plurality of bit lines, are detected and amplified simultaneously by said bit line sense amplifiers and said data line sense amplifier, for being rewritten in corresponding said memory cell, and data, which is not selected by said column selecting signal, of data read out to said a plurality of bit lines, are detected and amplified by only said bit line sense amplifiers, for being rewritten in corresponding said memory cell.
Specifically, data, which are selected by the column selecting gate, of data driven by the selected one of the word lines to be read out to the plurality of bit lines, may be detected and amplified simultaneously by the bit line sense amplifier and the data line sense amplifier to be rewritten in a corresponding one of the memory cells, and data, which are not selected by the column selecting gate, of data driven by the selected one of the word lines to be read out to the plurality of bit lines, may be detected and amplified by only the bit line sense amplifier to be rewritten in a corresponding one of the memory cells.
According to the present invention, the bit line sense amplifier and the data line sense amplifier are overlapped with each other to be activated to detect and amplify the bit line data, so that it is possible to carry out rapid data readout. That is, with the increase of the capacity of the bit line and the relative deterioration of the drive capacity of the bit line sense amplifier, the variation in amplitude of data read out to the bit line decreases. On the other hand, the data line sense
Ito Takashi
Kawase Tomokazu
Nakamura Ken'ichi
Yoshitani Yutaka
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Le Thong
Nelms David
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