Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-08-17

2001-07-24

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S189040, C365S230030

Reexamination Certificate

active

06266293

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a memory cell array arranged in a plurality of banks.
2. Description of the Related Art
A flash memory is one of electrically erasable and programmable read only memories (EEPROM), and is able to erase data stored therein, in a unit of sectors or blocks, In a memory cell array of such a flash memory, each of memory cell transistors is designed to have a floating gate, a control gate electrically connected to a word line extending from an X decoder, a drain electrically connected to a bit line and further to a data reading and writing circuit through a Y switch which is turned on or off by means of a Y decoder, and a source electrically connected to sources of other memory cells in the same sector and further to a source line control circuit which is called a source line switch or a source decoder circuit.
When programmed, a predetermined high voltage Vpp is applied to a control gate of a memory cell transistor, a voltage of about 5V is applied to a drain, and a source is grounded, to thereby introduce electrons into a floating gate.
When data is to be erased, a drain is made open, a control gate is grounded, and a voltage Vpp is applied to a source, to thereby draw electrons out of a floating gate.
When data is to be read out, a memory cell located at an intersection of a word line selected by an X decoder and a bit line electrically connected to a Y switch selected by a Y decoder is accessed. A current running through the bit line in accordance with a threshold voltage is read out through a data-reading circuit.
FIG. 1
is a block diagram of a conventional flash memory. The illustrated flash memory is comprised of a first stage circuit
301
, first and second transfer gates TG
1
and TG
2
, a latch circuit
302
comprised of first and second inverters INV
1
and INV
2
, and an inversion buffer INV
3
.
In the illustrated conventional flash memory, a memory cell array is generally designed to be arranged in a single bank. Hence, an address buffer which is designed to transmit an address signal to an X decoder circuit, a Y decoder circuit, and a source line control circuit, receives an external address and outputs the received external address as it is to the decoders.
Specifically, an external address signal is transmitted to an address decoder (not illustrated) as follows.
First, an external address signal is input into the first stage circuit
301
, and then, input into the latch circuit
302
through the second transfer gate TG
2
which is turned on or off in accordance with a latch control signal. An internal address is input into the latch circuit
302
through the first transfer gate TG
1
which is turned on when a data-erase flag is activated. The latch circuit
302
transmits an address buffer output signal to the address decoder through the inversion buffer INV
3
.
The latch circuit
302
is comprised of the first and second inverters INV
1
and INV
2
. An output terminal of the first inverter INV
1
is electrically connected to an input terminal of the second inverter INV
2
, and an output terminal of the second inverter INV
2
is electrically connected to an input terminal of the first inverter INV
1
. The first inverter INV
1
is comprised of a clocked inverter which is turned on or off in accordance with a latch control signal.
When a stand-by control signal is activated in the first stage circuit
301
, a current is disallowed to flow through the first stage circuit
301
regardless of a level of the external address.
When data is written into or read out of the flush memory, the latch control signal is activated, and the latch circuit
302
latches the external address input and transmits an address signal to the decoder circuit (not illustrated).
Data is automatically erased in the chip. Specifically, an internal address produced in the chip is input into the latch circuit
302
through the transfer gate TG
1
which is turned on when the data-erase flag is activated, and further into the source line control circuit. As a result, data is erased in each of the sectors.
The flash memory including the address buffer having the above-mentioned structure cannot read out data while the flash memory is writing data into or erasing data from a memory cell.
Recently, there has been suggested a semiconductor memory device including memory cells arranged in a plurality of banks. However, such a semiconductor memory device is accompanied with a problem that it is necessary to carry out address control in each of the banks, and hence, it is not avoidable for the semiconductor memory device to have an increased size.
If a flash memory is designed to have an arrangement where memory cells are arranged in a plurality of banks, the flush memory would be accompanied with the same problem as mentioned above.
For instance, Japanese Unexamined Patent Publication No. 11-86576 has suggested a flash memory including a memory cell array partitioned into two blocks, and data-reading circuits each associated with each of the memory cell blocks. Even when data is erased from the written into one of the memory cell blocks, data can be read out of or written into the other memory cell block. That is, the suggested flush memory has a function of dual operation.
In comparison with a flash memory having no function of dual operation, the suggested flash memory having the dual operation is designed to further include first and second data-reading circuits each associated with each of the memory cell blocks, a circuit for judging an address, a first multiplexer receiving outputs from the first and second data-reading circuits and transmitting an output to an output buffer circuit, and a second multiplexer receiving outputs from the first and second data-reading circuits and transmitting an output to a circuit for judging data is to be written into or erased from the memory.
The suggested flash memory can vary a bit arrangement in each of the memory cell blocks without an increase in complexity in a circuit and an increase in a chip area.
Japanese Unexamined Patent Publication No. 5-54682 has suggested a non-volatile semiconductor memory device including memory cells arranged in a plurality of blocks. The suggested semiconductor memory device can simultaneously erase data from one of the memory cell blocks and read data out of other memory cell block.
Japanese Unexamined Patent Publication No. 7-85657 has suggested a semiconductor memory device which is capable of reducing a peak current during flush-writing data, to thereby reduce consumption in a current.
Japanese Unexamined Patent Publication No. 10-326493 has suggested a flash memory device which is capable of simultaneously writing data thereinto or erasing data therefrom, and reading data out thereof.
Japanese Unexamined Patent Publication No. 11-134887 has suggested a column decoder circuit used for a flash memory circuit. The column decoder circuit has word lines partitioned into a plurality of blocks.
However, since the above-mentioned devices cannot switch addresses or blocks, the devices are accompanied with a problem that an address control has to be carried out in each of the addresses or blocks, and resultingly, it is not avoidable for the devices to be larger in a size.
SUMMARY OF THE INVENTION
In view of the above-mentioned problem in a conventional flush memory devices, it is an object of the present invention to provide a semiconductor memory device including memory cells arranged in a plurality of banks which device can be fabricated in a smaller size than the conventional one.
There is provided a semiconductor memory device including (a) a plurality of address recorders each associated with each of a plurality of banks, and (b) at least one address buffer circuit receiving an address signal as an input signal, and transmitting a bank address signal to each of the address recorders, the address buffer circuit transmitting a first address signal for reading

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