Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-06-13

2001-05-29

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185030, C365S185220, C365S201000

Reexamination Certificate

active

06240014

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 1999-23428, filed on Jun. 22, 1999, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and, more particularly, to a non-volatile semiconductor memory device with a multi-bit memory cell array.
BACKGROUND OF THE INVENTION
A conventional non-volatile memory cell includes a first terminal or a floating gate having high impedance and a second terminal or a MOS transistor having a control gate. Current electric memory circuits include thousands of cells that are integrated, with high packing rates, into a matrix shape in a semiconductor.
Because cells of a memory cell array are operated separately, each of the cells of a non-volatile memory chip needs to be able to receive programming or erasing signals. All of the cells are consequently required to have characteristics that lie within program operation and erasure operation minimum voltage margins. Different cells, however, have different threshold voltages for programming and erasing operations.
The ability to measure the distribution of threshold voltages (Vth) of (programmed and erased) memory cells is therefore very important to the fabricators and designers of memory devices. The density of threshold voltage distribution is a yardstick for determining whether memory arrangements are acceptable and whether state machines will smoothly perform their functions. To test the threshold voltage (Vth) of a memory cell, the gate voltage of a memory cell is supplied with a test voltage from the outside. In a memory circuit, the test voltage externally supplied to a cell terminal may be a program voltage.
FIG. 1
is a block diagram of a semiconductor memory device having a switching circuit
40
for testing the threshold voltage of a memory cell
20
. As shown in
FIG. 1
, a semiconductor memory device includes a test pad
10
, a memory cell array
20
, a row decoder
30
, a switching circuit
40
, and a word line voltage generation circuit
50
. The switching circuit
40
includes a PMOS transistor PM
1
, an NMOS transistor NM
1
, and an inverter INV
1
. During a test mode (when a test signal TE transitions to a high level), a test voltage from a test pad
10
is transferred to an output terminal
1
. The test voltage is supplied to a gate of a selected cell
20
through a row decoder
30
(via a word line VwL). When the test voltage causes the gate of the selected cell
20
to start turning on, then that test (gate) voltage is the threshold voltage (Vth) of the selected memory cell
20
.
When a test signal TE, applied to the word line voltage generation circuit
50
, is disabled to a low level (i.e., during a program verify mode), a word line voltage is supplied to a word line voltage output terminal
1
from the word line voltage generation circuit
50
. The word line voltage is then transferred to a selected word line through a row decoder
30
. During a program mode (or read mode), the row decoder
30
receives a program voltage Vpgrn (or read voltage Vread) from a program (or read) voltage generation circuit (not shown). The row decoder
30
then transfers the program voltage Vpgm (or read voltage Vread) to the selected word line
1
, while transferring a pass voltage Vpass to non-selected word lines.
FIG. 2
shows switching circuit
40
schematically and in a cross-sectional view. Referring now to
FIGS. 1 and 2
, the PMOS transistor PM
1
and the NMOS transistor NM
1
of the switching circuit
40
are formed as an N-well
62
and a P-well
64
, respectively, in a P-type substrate
60
. The N-well
62
is coupled to a low power supply voltage Vcc (e.g., 2.1V or less), and the P-well is coupled to a ground GND.
In the switching circuit
40
of a memory device having multi-bit memory cells
20
, when a test signal TE is disabled (for example, during a program verify mode), a voltage of 0.4V, 1.6V, or 2.8V is supplied to the selected word line in a state of “10”, “01”, or “00”, respectively. A voltage of 0.8V-1.0V, on the other hand, is supplied to a word line of a single-bit memory cell during program verify operation.
In operation, when the test signal TE is disabled, the PMOS transistor PM
1
and the NMOS transistor NM
1
of the switching circuit
40
are turned off. A voltage (2.2V in a state of “
00
”) is supplied to the output terminal
1
of a word line voltage generation circuit
50
, and a low power supply voltage of about 2.1V or less is supplied to the N-well
62
. A PN diode D
1
is consequently turned on between a source
66
b
(connected to V
WL
) and the well
62
of the PMOS transistor coupled to the word line voltage output terminal
1
, so that leakage current flows. This leakage current makes it impossible to verify a normal program operation under these conditions.
SUMMARY OF THE INVENTION
The present invention solves the problem of leakage current by providing a memory device capable of interrupting the leakage current path between the switching circuit and the word line output terminal during a normal operation mode.
According to one aspect of the invention, a semiconductor memory device includes a memory cell array, a row decoder, a first switching circuit, and a second switching circuit. The memory cell array has a plurality of memory cells, each coupled to a word line among a plurality of word lines. During a normal operation mode, a word line voltage generation circuit generates a word line voltage. The row decoder selects one of the word lines and supplies the word line voltage to the selected word line. The first switching circuit is coupled to a test pad, and supplies an external test voltage to the word line voltage output terminal. The second switching circuit is coupled between the first switching circuit and the word line voltage output terminal and is configured such that, if a voltage level of a word line voltage terminal is higher than that of a power supply voltage, it interrupts the current path from the word line voltage output terminal to the first switching circuit.
In a preferred embodiment, the normal operation mode is a program verify mode and each of the memory cells is a multi-bit memory cell. The second switching circuit, according to this embodiment, includes a depletion-type transistor having a gate that receives the test signal and a channel coupled between the first switching circuit and the word line voltage output terminal. When a signal informing the test mode is enabled, the second switching circuit supplies a test voltage to the word line voltage output terminal. When the signal is disabled, an output terminal voltage of the word line voltage generation circuit is higher than a power supply voltage causing the second switching circuit to interrupt the coupling between the word line voltage output terminal and the first switching circuit.
According to another embodiment of this invention, a semiconductor memory device has a plurality of word lines, a memory cell array, a row decoder, a switching circuit, and a word line voltage generation circuit. The memory cell array includes a plurality of memory cells, each coupled to one of the word lines. The row decoder selects one of the word lines and the switching circuit supplies an external test voltage to the selected word line through the row decoder in response to a first and a second test signals. The word line voltage generation circuit supplies a voltage to the selected word line through the row decoder during a program verify mode. The switching circuit includes a first transistor, a second transistor, and a third transistor. The first transistor has a gate that receives the second test signal, and a source/drain formed at a second conductive well in a first conductive substrate. The second transistor has a gate that receives the first test signal, and a source/drain formed in a first conductive well at a distance from the second conductive well. The third transistor has a gate that receives the first test signal and a source/drain formed on th

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