Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-04-14

2001-08-14

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S189040

Reexamination Certificate

active

06275423

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device for reading data of a number of bits from its memory cell region simultaneously and successively outputting the read data to an external environment.
2. Description of the Related Art
Some semiconductor memory devices, such as dynamic random access memory (DRAM) devices read data of a number of bits simultaneously in one read step and successively output data of the accessed bits in synchronization with the rise and fall phases of the pulse signals of a system reference clock. In such a semiconductor memory device, a given number of parallel bit-data to be accessed are converted into serial data to be output at each rise and fall phase of the system reference clock to be output externally, and the converted serial data are alternately multiplexed to obtain an internal data processing period that is double the data output period of the memory device to produce high speed serial output data to be transmitted to an external system.
FIG. 9
shows a schematic diagram of such a semiconductor memory device. A memory cell array
100
is comprised by a large number of memory cells arranged in an array, where each of the bit-data for rise phases and fall phases of the system reference clock is stored in a predetermined cell location in the array. These stored bit-data contain the data corresponding to the bits for the rise phases and the fall phases, and the burst length, which defines the number of bits that can be exchanged (input/output) in one operation (one write/read step) between the memory cell array
100
and the external environment, is a predetermined quantity. In general, such data are referred to as even data when the data are processed during the rise phase of the clock pulses of the system reference clock, and as odd data when the data are processed during the fall phase of the clock pulses of the system
Data-amps
101
are provided to amplify the bit-data of several bits output in one read step. If the number of bits is eight, eight amplifiers will be provided as shown in the diagram so that each bit can be assigned to one amplifier. For a read step, each data-amp is activated by a data-amp-enable signal DAE so that each bit-data output from the memory cell array
100
is amplified to be supplied to the parallel-serial conversion circuit
102
e
or
102
o
for even data or odd data, respectively. Parallel 4-bit even data amplified by the four data-amps shown on the right side of
FIG. 9
are input into the parallel-serial conversion circuit
102
e
(DM
10
, DM
12
, DM
14
, DM
16
in
FIG. 9
refer to those even data), and are output as serial 4-bit even data. On the other hand, parallel 4-bit odd data amplified by the four data-amps shown on the left side of
FIG. 9
are input into the parallel-serial conversion circuit
102
o
(DM
11
, DM
13
, DM
15
, DM
17
in
FIG. 9
refer to those odd data), and are output as serial 4-bit odd data.
In the memory device having such a structure, for read operation, data are read from the memory cell array
100
and are supplied to the data-amps
101
, which are activated so that the read data are amplified to a predetermined signal level. The 4-bit even data DM
10
, DM
12
, DM
14
, DM
16
of the read data are supplied to the parallel-serial conversion circuit
102
e
, and are output successively by being synchronized to the falls of the internal clock of the memory device. On the other hand, the 4-bit odd data DM
11
, DM
13
, DM
15
, DM
17
of the read data are supplied to the parallel-serial conversion circuit
102
o
, and are output successively in synchronization with the rises of the internal clock of the memory device. In this way, because there is no restriction on which phase of the internal clock pulse (rise or fall phase) to use to process even and odd data in the memory device, the data processing timing within the memory device may be inverted with respect to the external data processing timing.
Accordingly, serialized even data and odd data are supplied to a multiplexer (not shown). The multiplexer selects even data and odd data alternately at the rise and fall phases of the system reference clock, and the selected data are output to specific input/output pad successively, thereby outputting high speed serial bit-data containing 1 bit in each data at the rise and fall phases.
In the field of technology of applications of semiconductor memory devices described above, it is sometimes necessary to select and output a certain specific bit (or bits) of the group of bits to be read in one step. For example, in an arrangement of the memory devices M
1
, M
2
, M
3
, . . . MN, . . . to output wired-or output DOR on rise and fall phases of the system reference clock, as shown in
FIG. 10
, it is sometimes desired to select and output read data of a certain specific bit from one of the memory devices for each 1-bit transfer cycle.
An example of the timing for such an output process is shown in FIG.
11
. In this diagram, CLK refers to a reference clock (the system reference clock of the external environment) to operate the system containing the semiconductor memory devices M
1
, M
2
, M
3
, . . . , MN, . . . , each of which selects and outputs one bit of read data at every rise/fall phase independently. An example of the process is such that, at the instant of the first rise of the reference clock CLK after the beginning of the read operation, read data DM
10
selected in M
1
is output as output DOR, and at the instant of the first fall following the first rise, read data DM
31
selected in M
3
is output as output DOR, and at the instant of the second rise following the first fall, read data M
82
selected in M
8
is output as output DOR, and so on, so that any selected read data stored in the memory device can be output at any data transfer cycle to obtain output strings of output DOR shown in FIG.
11
. In such a case, it is necessary that the memory devices M
1
, M
2
, M
3
, . . . , MN, . . . are all synchronized to the same external system reference clock and each memory device is accessed in the order of sequence M
1
, M
3
, M
8
, ., M
2
, . so that the data are output in the sequence M
1
, M
3
, M
8
, ., M
2
, . as illustrated in the diagram.
However, in the conventional memory devices described above, because the number of bits to be output in one read-step is predetermined, once the read step has been initiated, the read process cannot be stopped until all the serial data of the burst length consisting of the specified number of bits are output. Therefore, the first accessed memory device M
1
outputs bit-
0
as output DOR but the succeeding bit-
1
to bit-
7
are also output, and in the second accessed memory device M
3
, after bit-
0
is output bit-
1
is output as output DOR, followed by the succeeding bit-
2
to bit-
7
. For the succeeding accessed memory devices, although the specified bits are output as output DOR, other bits included in the burst length are also output. For this reason, output sequence such as the one shown in
FIG. 11
cannot be produced by simply connecting conventional semiconductor memory devices.
A conventional approach for resolving such a problem is known as the “chip selection method”, in which a specific chip of the memory devices is selected and only the specified bit-data in the selected chip is output. This approach is practical only when the reference clock cycle is slow so that the data, as shown in
FIG. 11
, are output at relatively low speed.
However, in the chip selection method, only those cells specified by an external addressing device in certain memory devices can output a specified bit-data and other bit-data are floated so that they cannot be output externally. Such a method cannot produce the results shown in
FIG. 11
when the operating frequency of the system reference clock is high. That is, because the read addresses are supplied at a high speed of the system reference clock, it becomes difficult to generate a condition to output only a specific bit from a

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