Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-01-24

2001-04-17

Phan, Trong (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000

Reexamination Certificate

active

06219271

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device in which a memory cell has a CMOS (Complementary Metal Oxide Semiconductor) configuration, such as a SRAM (Static Random Access Memory) cell with a six-transistor configuration.
2. Description of the Related Art
A SRAM cell generally has a latch and two transistors (word transistors). On-off operations of the transistors are controlled based on the voltage applied to a word line and thereby connection between each of two memory nodes of the latch and a bit line is made or broken. SRAM cells can be broadly divided into two types, namely, a MOS transistor load type and a high resistance load type; where the difference is based on a load element of the latch. SRAM cells of the MOS transistor load type, configured with six transistors, can be further broken down into two known types: a P-channel MOS transistor (called pMOS in the followings) load type and a TFT (Thin Film Transistor) load type, depending on the type of its load transistor.
FIG. 5
shows an example of a configuration pattern of a SRAM cell of the pMOS load type according to the related art. In
FIG. 5
, a SRAM cell is shown provided with a gate of the transistor. Wire connection inside the cell or upper wiring layers such as bit lines are omitted. Instead,
FIG. 5
discloses the connection between portions effected by the upper wiring layers together with the pattern diagram.
The SRAM cell
100
of the pMOS load type has two p-type active regions
101
a
and
101
b,
and two n-type MOS active regions
102
a
and
102
b.
In the p-type active regions
101
a
and
101
b,
an n-channel MOS transistor (called nMOS in the followings) as a drive transistor is formed. In the n-type active regions
102
a
and
102
b,
a p-channel MOS transistor (called pMOS in the followings) as a load transistor is formed. The p-type active regions
101
a
and
101
b,
and the n-type active regions
102
a
and
102
b
are surrounded by an element separation insulating region of LOCOS (Local Oxidation of Silicon) or trench construction, for example.
In the SRAM cell
100
of the related art, the two p-type active regions
101
a
and
101
b
are turned outward approximately at a right angle in plan configuration. In the p-type active region
101
a,
a drive transistor Qn
1
and a word transistor Qn
3
are formed on both turned ends, sandwiching the bend. In the p-type active region
101
b,
a drive transistor Qn
2
and a word transistor Qn
4
are formed on both turned ends, sandwiching the bend. A word line (WL)
104
, which also works as gate electrodes of the word transistors Qn
3
and Qn
4
, is substantially orthogonal to both of the p-type active regions
101
a
and
101
b.
The word line
104
is provided through cells in the horizontal direction as shown in FIG.
5
. On the other hand, common gate lines
103
a
and
103
b,
which work as gate electrodes of the drive transistors Qn
1
and Qn
2
, are provided to each cell separately. The common gate line
103
a
is provided in the vertical direction as shown in FIG.
5
and orthogonal to the p-type active region
101
a.
The common gate line
103
b
is provided in the same direction and orthogonal to the p-type active region
101
b.
The common gate lines
103
a
and
103
b
are also orthogonal to the n-type active region
102
a
and
102
b,
respectively. Thereby, pMOS transistors (load transistors Qp
1
and Qp
2
) are formed in the n-type active regions
102
a
and
102
b,
respectively. The load transistor Qp
1
and the drive transistor Qn
1
constitute a first inverter. The load transistor Qp
2
and the drive transistor Qn
2
constitute a second inverter. The first inverter and the second inverter constitute a latch. Each of the common gate lines
103
a
and
103
b
branches off at some mid point. As shown in the connection in
FIG. 5
, an input terminal of one inverter is connected to an output terminal of another inverter by a second wiring layer. Further, a Vcc (source voltage) supply line
105
a,
a Vss (common potential) supply line
105
b,
a bit line (BL
1
)
106
a
and a bit line (BL
2
)
106
b
are connected as shown.
Generally, in the SRAM cell with the above-described six-transistor configuration of the related art, DTw/WTw=1.0 and LTw/WTw=1.0, where DTw denotes a channel width of the drive transistors Qn
1
and Qn
2
, WTw denotes a channel width of the word transistors Qn
3
and Qn
4
, and LTw denotes a channel width of the load transistors Qp
1
and Qp
2
. In other words, the channel width of the drive transistors Qn
1
and Qn
2
and the channel width of the load transistors Qp
1
and Qp
2
are made to be equal to the channel width of the word transistors Qn
3
and Qn
4
.
However, in the case of a SRAM aimed for high-speed operations, a large cell current is required in order to minimize a delay in a bit line. As a result, an increase in the channel width WTw of the word transistors is needed. Thus, designing the SRAM cell while maintaining the above-described relationship, DTw/WTw=1.0 and LTw/WTw=1.0, causes an increase in, especially, the channel width LTw of the load transistors Qp
1
and Qp
2
, which are the only load transistors within the cell. This results in an increase in a cell size in a direction of the bit line, causing a problem in high integration.
The present invention is made in view of such a problem. An object of the invention is to provide a semiconductor memory device making it possible to reduce the size of memory cells and to achieve higher integration.
A semiconductor memory device according to the present invention comprises a plurality of memory cells, where each memory cell is provided with a pair of drive transistors of a first conductive type, a pair of load transistors of a second conductive type and a pair of word transistors of the first conductive type, wherein the relationship between a channel width DTw of the drive transistors and a channel width LTw of the load transistors is given by DTw/LTw>1.0, more preferably, DTw/LTw>1.4.
Particularly, the semiconductor memory device according to the present invention is suitable for a SRAM comprising a first active region in which a channel of the drive transistor and a channel of the word transistor are formed, a second active region in which a channel of the load transistor is formed, a word line which works as å gate electrode of the word transistor, and a common gate line which connects between a gate of the drive transistor and a gate of the load transistor, wherein a channel current direction of the drive transistor and a channel current direction of the word transistor are orthogonal to each other in the first active region, the word line is orthogonal to the first active region, and the common gate line is orthogonal both to the first active region and to the second active region.
In the semiconductor memory device according to the present invention, the channel width DTw of the drive transistor is made greater than the channel width LTw of the load transistor. Accordingly, the cell size can be reduced, as compared to the case with a semiconductor memory device of the related art with the relationship of DTw/LTw=1.
Other and Further objects, features and advantages of the invention will appear more fully from the following description.


REFERENCES:
patent: 5222039 (1993-06-01), Vinal
patent: 5379251 (1995-01-01), Takeda et al.
patent: 5384731 (1995-01-01), Kuriyama et al.
patent: 5732015 (1998-03-01), Kazerounian et al.
patent: 5793670 (1998-08-01), Wada et al.
patent: 5808942 (1998-09-01), Sharpe-Geisler

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