Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-05-26

2001-09-11

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S230030

Reexamination Certificate

active

06288930

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device. More particularly, this invention relates to a non-volatile ferroelectric memory (Ferroelectric RAM, henceforth, FeRAM). This FeRAM is obtained by using a ferroelectric in a capacitor section of a DRAM. Since data is stored with remanence of this capacitor section, the data can be held without a power source to hold data. Therefore, a FeRAM is sometimes used to store cipher and secret code (henceforth, cipher or the like) in an IC card or the like.
BACKGROUND OF THE INVENTION
FIG. 1
is a schematic diagram showing connections between memory cells, word lines, and plate lines in a conventional FeRAM.
FIG. 2
is a schematic diagram showing connections between the memory cells and bit lines in the conventional FeRAM.
As shown in
FIG. 1
, a pair of row selection lines, consisting of a word line W and a plate line P, are connected to a group of memory cells in the row direction (henceforth, a memory-cell row) in a one-to-one relationship in the conventional FeRAM. Namely, in
FIG. 1
, a pair of first-row selection lines W
1
and P
1
are connected to memory cells
11
,
12
,
13
, . . . in the first row. A pair of second-row selection lines W
2
and P
2
are connected to memory cells
21
,
22
,
23
, . . . in the second row. A pair of third-row selection lines W
3
and P
3
are connected to memory cells
31
,
32
,
33
, . . . in the third row.
As shown in
FIG. 2
, a pair of column selection lines, consisting of a pair of bit lines B and B, are connected to a group of memory cells in the column direction (henceforth, a memory-cell column) in a one-to-one relationship in the conventional FeRAM. Namely, in
FIG. 2
, a pair of first-column selection lines B
11
and B
12
are connected to the memory cells
11
,
21
, . . . in the first column. A pair of second-column selection lines B
21
and B
22
are connected to the memory cells
12
,
22
, . . . in the second column. A pair of third-column selection lines B
31
and B
32
are connected to the memory cells
13
,
23
, . . . in the third column. A pair of fourth-column selection lines B
41
and B
42
are connected to the memory cells
14
,
24
, . . . in the fourth column.
Let us consider a case of the FeRAM in which memory cells are formed with two transistors and two ferroelectric elements (ferroelectric capacitors). In such a FeRAM, the memory cells are structured as shown in FIG.
3
. Namely, one electrode of each of the two ferroelectric elements C
1
and C
2
in each of the memory cells
11
,
12
, . . . ,
21
,
22
, . . . are connected to different transistors Q
1
and Q
2
. Whereas the other electrodes of the ferroelectric elements C
1
and C
2
are connected to the plate lines P
1
and P
2
, respectively.
When the FeRAM is to be fabricated, it is generally required to write cipher or the like in a memory cell that consists of ferroelectric elements in the stage of wafer process of the fabrication process. That is because it is not preferable from the viewpoint of data security that the write operation is performed after the completed FeRAM-chip package has been mounted on a circuit board.
It has been known that external factors such as heat or hydrogen cause degradation in the characteristics of the ferroelectric element. Accordingly, even if the cipher or the like are written in the ferroelectric memory cell in the wafer process, memory information may be lost due to degradation in the characteristics of the ferroelectric memory cell. More specifically, this degradation is caused by the fact that the ferroelectric element is affected by heat or when exposed to hydrogen during the fabrication process after the write operation has been performed. The loss of stored information is a great disadvantage from the viewpoint of reliability.
During the conventional fabrication process as explained above, however, the external factors such as heat or hydrogen need to be removed as much as possible. Therefore, the fabrication process is restricted by this requirement. Further, some facilities to eliminate the influence of heat or hydrogen on the process are needed, which is different from the manufacturing facilities of an ordinary DRAM or the like. Thus, the manufacturing cost increases, which results in the costly FeRAM package.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a semiconductor memory device with ferroelectric memory cells that hold memory information even if the ferroelectric elements are affected by heat or hydrogen in the fabrication process.
According to one aspect of this invention, the semiconductor memory device with ferroelectric memory cells comprises a first ferroelectric memory cell in which data is written after the device has been mounted on aboard. The semiconductor memory device further comprises a second ferroelectric memory cell, whose capacitance is larger as compared to that of the first ferroelectric memory cell. This second ferroelectric memory cell is utilized as a memory cell in which cipher or the like are written in the fabrication process.
The characteristics of the ferroelectric are determined according to a large or a small amount of capacitance of the ferroelectric. Therefore, if the cipher or the like are written in the second ferroelectric memory cell which has a larger amount of capacitance in the fabrication process, the ferroelectric memory cell can still hold the memory information even after the fabrication has been completed. The reason is, even if the ferroelectric is affected by heat or exposed to hydrogen during fabrication, the characteristics of the memory cell are not degraded to such a level that the memory information is lost.
The second ferroelectric memory cell may be formed with a combination of a plurality of first ferroelectric memory cells. Further, when the first ferroelectric memory cell has a plurality of ferroelectric capacitors (ferroelectric elements), the second ferroelectric memory cell may be formed by connecting the plurality of ferroelectric capacitors included in the first ferroelectric memory cell in parallel to each another. Based on this configuration, the capacitance of the second ferroelectric memory cell can be increased to a larger amount as compared to that of the first ferroelectric memory cell.
More specifically, when the second ferroelectric memory cell is formed with a plurality of first ferroelectric memory cells, a plurality of row selection lines (word lines, plate lines) or a plurality of column selection lines (bit lines) are short-circuited. Based on this configuration, the same information is written in the plurality of first ferroelectric memory cells in which the row selection lines (word lines, plate lines) are short-circuited. Therefore, the information written in the second ferroelectric memory cell is held in the ferroelectric memory cell, which has the capacitance a plurality of times as large as the capacitance in the case where the information is written in the first ferroelectric memory cell. Accordingly, the memory information can be held even when the ferroelectric memory cell is affected by heat or hydrogen during fabrication. The same effect can also be obtained in the case where the column selection lines (bit lines) are short-circuited.
A selection circuit may be provided. Any row selection lines (word lines, plate lines) or column selection lines (bit lines) to be short-circuited may also be selected by this selection circuit. Based on this configuration, any row selection lines (word lines, plate lines) or column selection lines (bit lines) to be short-circuited can be changed according to the amount of data such as cipher or the like to be written.
Further, a program, with which any row selection lines (word lines, plate lines) or column selection lines (bit lines) to be short-circuited are selected, may be stored in a storage unit (program storage section) such as a ROM. A control unit (program control circuit), that selects a plurality of row selection lines (word lines, plate lines) or a plurality of colu

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