Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-06-13

2001-09-11

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189090, C365S226000, C365S227000

Reexamination Certificate

active

06288963

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as a dynamic random access memory (DRAM, hereinafter) requiring refresh operation which is an operation for recharging electric charge periodically so as to retain electric charge accumulated in a memory cell, and more particularly, to a semiconductor memory device in which power consumption in the dormant state where only the recharging is carried out can be reduced, thereby to be able to use for a long time when installed in various portable equipments.
2. Description of Related Art
In recent years, many high-speed memories having large capacities are mounted in various portable equipments such as a notebook personal computer and a mobile personal computer as functionality is advancing. The DRAM is a typical memory, and is used as a standard memory of the portable equipment because of its large capacity and high speed.
On the other hand, the portable equipment itself is required to operate for a long time with one charge and is required that the power consumption of its components is small. In the case of the DRAM, it is necessary to periodically refresh for retaining electric charge accumulated in its memory cell, and to recharge the electric charge accumulated in the memory cell, and electric power is consumed even in the dormant state where data are not input or output. Therefore, in order to reduce the power consumption of the portable equipment, it is also necessary to reduce the power consumption at the time of refresh operation of the DRAM.
So as to meet the above requirement, in the DRAM, a refresh operation for reducing the power consumption in a so-called data retention mode in the dormant state is carried out. The data retention mode will be explained below with reference to
FIGS. 38
to
43
.
FIG. 38
shows a circuit block diagram
300
of a DRAM. A control circuit
301
receives external signals such as /RAS (Row Address Strobe) signal, /CAS (Column Address Strobe) signal, /WE (Write Enable) signal, CLK (Clock) signal, /CS (Chip Select) signal and the like, and controls input of address, input and output of data, refresh control and the like. A column decoder
302
connects a bit line (BL) selected by a column address (CA) to a data bus (not shown), thereby inputting and outputting data. An internal reduced voltage generating circuit
303
is mounted in the DRAM for reducing an external power supply voltage when mismatch is generated between an external power supply voltage and a power supply voltage required for a device as the packing density is increased. A substrate voltage generating circuit
304
is a circuit for generating voltage for biasing a substrate portion in a memory cell array
305
to negative voltage because of a reason which will be mentioned later.
In the DRAM, a memory cell group is disposed on the memory cell array
305
in a matrix manner, and a large number of memory cells are connected to a word line (WL in the drawing) selected in correspondence with a row address signal. This memory cell array
305
comprises six, for example, blocks BLK
1
to BLK
6
. At the time of the refresh operation, row address (RAref) to be refreshed by a refresh address counter circuit
307
is counted up based on a refresh cycle set by a refresh timer circuit
306
, and is supplied to a row address selecting circuit
308
. The row address selecting circuit
308
selects the refresh row address (RAref), a part of the refresh row address (RAref) is supplied to a cell array block selecting circuit
309
, and the remainder is supplied to a word line selecting circuit
310
. A word line driving circuit
311
activates a word line in the block corresponding to the refresh address (RAref) in response to outputs of the cell array block selecting circuit
309
and the word line selecting circuit
310
.
Electric charge in a memory cell connected to the selected word line WL is read out to the bit line BL, and is amplified by a sense amplifier (not shown) so that the amount of electric charge accumulated in the memory cell is restored. This refresh operation is carried out by selecting the word lines WL in sequence within a time period during which the electric charge in the memory cell is retained in the memory cell.
FIG. 39
schematically shows the positional relation among the memory cell
313
, the word lines WL and bit lines BL (BL
1
, /BL
1
, /BL
2
in
FIG. 39
) in the memory cell array
305
.
FIG. 39
shows a region B in
FIG. 38
in enlarged scale. In
FIG. 39
, symbols ◯ represent memory cells
313
. A memory cell group intersecting the word line WL is selected by the word line WL, and electric charge is input and output on the intersecting bit lines BL (BL
1
, /BL
1
, /BL
2
in FIG.
39
). The memory cells
313
are laid out in a staggered arrangement manner, and the positional relation among the memory cells
313
including the word lines WL, bit lines BL (BL
1
, /BL
1
, /BL
2
in
FIG. 39
) and the like is most densely integrated.
A cross section structure of the memory cell
313
along the bit line BL
1
in
FIG. 39
is shown in FIG.
40
. Each of M
1
and M
2
of the memory cell
313
comprises one NMOS transistor
315
formed on a P-type substrate
314
and one cell capacitor
316
, surroundings thereof are separated from adjacent cells by thick field oxide layers
317
. The adjacent cells are disposed in a back-to-back manner through the field oxide layers
317
, and WL
2
of the word line WL which selects memory cells
313
which are adjacent in the vertical direction in
FIG. 40
are disposed on the field oxide layers
317
. In the memory cell
313
of this structure, electric charge as the data is accumulated in the cell capacitor
316
, and the input and output as well as the retention of the electric charge are conducted by switching the NMOS transistor
315
.
In recent years, when a substrate is grounded, a threshold voltage of the NMOS transistor is about 0.4 V due to the progression of packing density, but with such a low threshold voltage, the amount of accumulated electric charge is reduced by a leak current from the cell capacitor
316
through the switching NMOS transistor
315
of the memory cell
313
, and it is not preferable in terms of electric charge retention characteristics in some cases. Further, due to a structure in view of a layout of the memory cell
313
, the NMOS transistor (field MOS transistor, hereinafter, MF
1
in
FIGS. 39 and 40
) is formed such that diffusion layers of the adjacent cell capacitors
316
sandwiches the field oxide layer
317
, and the WL
2
of the word line WL on the field oxide layer
317
is used as a gate. Due to the progression of packing density, a threshold voltage of the field MOS transistor MF
1
tends to be shallower, and in a state where the substrate has grounded potential, the current leak (leak current (
2
) in
FIG. 40
) between the adjacent cell capacitors
316
by driving of WL
2
of other word line WL may induce some problems, and this is known as a so-called disturb problem. To solve the above problem, in recent DRAM, threshold voltage of the switching NMOS transistor
315
and the field MOS transistor MF
1
are set deep utilizing a substrate bias effect of the MOS transistor by biasing negative voltage VBB to the substrate
314
, thereby preventing the leak current and the like.
Here, the purpose of the refresh operation is achieved by amplifying the electric charge of the cell capacitor
316
read out on a bit line BL without inputting or outputting data, and again charging the electric charge to the cell capacitor. Concerning the frequency of this operation, the operation cycle may be set long within a range of produce specification in accordance with the electric charge retention ability of the memory cell
313
, and unlike the normal data input and output operation requiring high access speed, high speed of the operation is not required.
That is, in the refresh operation, the power supply voltage can be reduced and as a result, voltage applied to the word

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