Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-07-25

2001-07-31

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S200000, C365S230080

Reexamination Certificate

active

06269030

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in Japanese Patent Application No. H11-210295 filed on Jul. 26, 1999 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates generally to a semiconductor memory device adopting a redundant circuit system for relieving defects in memory cells.
In semiconductor memories, such as DRAMs, defective cell rows and/or defective cell columns of a memory cell array are generally replaced with redundant cell rows and/or redundant cell columns to be relieved. Hereinafter, cell rows and cell columns are simply referred to as rows and columns, respectively.
In order to achieve this, a cell array including redundant rows and redundant columns, together with an address comparator circuit, is provided in a chip.
In the address comparator circuit, a defective address is programmed on the basis of test (die sorting test) results performed in a wafer state. Then, the address comparator circuit has the function of outputting a substitute signal when an inputted address is coincident with the programmed defective address, to select a redundant row or a redundant column in place of a defective row or a defective column. Hereinafter, a redundant row or a redundant column is referred as a redundant element if distinction is not necessary.
A typical defective address storing circuit of the address comparator circuit uses a fuse circuit wherein a programming is carried out by laser light. After the programming in the address comparator circuit, non-defective memory chips are cut away from a wafer to be assembled into packages. Thereafter, a stress test is carried out, and finally, a memory test (a shipping test) is carried out whether the memory is normally operated. Only non-defective memories having passed the memory test are shipped, and the rest of the memories are discarded.
Conventionally, a fuse element blown by laser light has been used as the address comparator circuit, and there has been no means for relieving defects found in a test after assembly.
Therefore, in order to improve the yields of memories, it is important to precisely carry out a wafer process to enhance the yields in a die sorting test and to reduce the number of chips discarded by a shipping test. However, conventional semiconductor memories are not provided with any means for relieving defects generated after assembly.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a semiconductor memory device capable of relieving defects generated after assembly.
According to one aspect of the present invention, there is provided a semiconductor memory device comprising:
a memory cell array;
a plurality of redundant elements for relieving defective memory cells of said memory cell array;
a decode circuit for decoding an input address to select a memory cell of said memory cell array;
a first address comparator circuit capable of carrying out a programming using laser light in a wafer state, for outputting a substitute signal for selecting one of said plurality of redundant elements with respect to a defective address detected in the wafer state; and
a second address comparator circuit capable of electrically carrying out a programming after assembly, for outputting a substitute signal for selecting another of said plurality of redundant elements with respect to a defective address detected after a chip is assembled.
According to the present invention, a first address comparator circuit for carrying out a programming in a wafer state, together with a second address comparator circuit capable of carrying out a programming after assembly, is provided, so that it is possible to relieve defects, which are produced in a test after assembly, to enhance the relief efficiency for memories.
If a test circuit for detecting defects of a plurality of redundant elements is provided according to the present invention, it is possible to avoid a defective redundant element when a programming is carried out in the second address comparator circuit.
According to a second aspect of the present invention, there is provided a semiconductor memory device comprising:
a memory cell array which is divided into a plurality of cell array blocks;
first and second groups of redundant elements, each group of said redundant elements being arranged for each of said cell array blocks so as to relief a defective memory cell in a corresponding one of said cell array blocks;
a decode circuit for decoding an input address to select a memory cell of said memory cell array;
a first address comparator circuit capable of carrying out a programming using laser light in a wafer state, for outputting a substitute signal for selecting one of said plurality of redundant elements with respect to a defective address detected in the wafer state; and
a second address comparator circuit capable of electrically carrying out a programming after assembly, for outputting a substitute signal for selecting another of said plurality of redundant elements with respect to a defective address detected after a chip is assembled,
wherein said first address comparator circuit is shared by said plurality of cell array blocks to be capable of flexibly corresponding to said first group of redundant elements of each of said cell array blocks, and
said second address comparator circuit is shared by said plurality of cell array blocks to be capable of flexibly corresponding to said second group of redundant elements of each of said cell array blocks.


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patent: 5631868 (1997-05-01), Termullo, Jr. et al.
patent: 6018811 (2000-01-01), Merritt
patent: 6115300 (2000-09-01), Massoumi et al.
patent: 8-235892 (1996-09-01), None

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