Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1999-12-28

2001-06-05

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S203000, C365S205000, C365S191000, C365S196000, C365S204000

Reexamination Certificate

active

06243312

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, it relates to a semiconductor memory device which feeds back a signal made by detecting a data sensing when reading a memory chip, precharges a local data bus within a short time, performs a high-speed operation, and enhances a burst characteristic and AC characteristic responsive to the burst characteristic.
2. Description of the Prior Art
There is a burst read operation for making a high-speed operation in a synchronous dynamic random access memory (SDRAM) or a high-speed memory. If an external row active command and a read command are received, a data as many as a predetermined burst length (BL) is successively generated through a DQ pin according to an external clock. This is called a burst read operation.
For example, in case that a burst length BL is set to 4 as shown in
FIG. 1
illustrating a timing diagram of a read operation in case of a burst length (BL)=4 and clock latency (CL)=2, four data are successively generated in response to an external clock by a read command. Here, a clock latency (CAS latency) of 2 means that a first data is generated after two clocks after a read command is received.
Such operation will be described with reference to FIG.
2
.
FIG. 2
is a block diagram of a prior semiconductor memory device related to a data bus for a read operation.
Referring to
FIG. 2
, under a row active state, a column command and a clock signal (hereinafter referred to as E_CLK) internally made by an external clock are input to a CAS control unit
10
.
A burst length counter unit
20
counts internal clocks I_CLK generated from the CAS control unit
10
, and transmits enable signals BSC as many as a burst length BL to the CAS control unit
10
, thereby generating internal clocks I_CLK as many as the burst length. Namely, in case of a burst length (BL)=4, four internal clocks are successively generated.
Two signals PYL and PRC are generated from a column precharge control unit
30
by the internal clock I_CLK.
A signal PYI is input to a column decoder unit
40
, and thus makes a column decoder output signal Yi selecting a bit line sense-amplifier unit
50
along with a column address. The bit line sense-amplifier unit
50
including a cell data amplified by a row active command transmits the cell data to a local data bus when receiving the column decoder output signal Yi. The column decoder unit output signal Yi is generally generated as a pulse.
The data loaded on the local data bus is transmitted to the data bus sense-amplifier unit
70
. At this time, once sensing operation is achieved, and thus the data is transmitted to a global data bus.
A signal PRC made by the internal clock I_CLK in the column precharge control unit
30
precharges a local data bus with a local data bus precharge voltage Vprc, and makes the data bus sense-amplifier
70
be at a precharge/standby state.
Before the column decoder unit output signal Yi opens the bit line sense-amplifier
50
toward the local data bus, the signal PRC prevents a precharge of the local data bus, and makes the data bus sense-amplifier unit
70
be at an active state.
After that, if the column decoder output signal Yi is enabled, the data is transmitted to the global data bus. If the column decoder unit output signal Yi is disabled, the bit line sense-amplifier unit
50
is closed, the signal PRC precharges the local data bus, and makes the data bus sense-amplifier unit
70
be at a precharge/standby state.
Herein, a column precharge control unit
30
adjusts each timing of the column decoder unit output signal Yi and the signal PRC by using the internal clock I_CLK. Accordingly, amplitudes of the column decoder unit output signal Yi and the signal PRC are determined in the column precharge control unit
30
. In case of a burst read operation, an operation that a data as much as a burst length BL is loaded on the local data bus or is precharged is repeated.
FIG. 3
is a timing diagram of a signal and data in case of a read operation about a low clock frequency of
FIG. 2
; and
FIG. 4
is a timing diagram of a signal and data in case of a read operation about a high clock frequency of FIG.
2
.
FIGS. 3-4
illustrate an example that data of another phase is successively loaded.
Let us suppose that a bit line sense-amplifier unit
50
is opened in case of a column decoder unit output signal Yi of a high state, and a precharge of a local data bus is prevented and a bus sense-amplifier unit
70
is activated in case of a signal PRC of a high state.
If the signal PRC and the column decoder unit output signal Yi are enabled as a high state, a local data is generated and thus a global data is generated from the data bus sense-amplifier unit
70
.
In this case, there is no problem to read the data in case of a low clock frequency as shown in FIG.
3
. That is, a read/precharge operation about one data and a read/precharge operation about the next data are normally performed. However, as a clock frequency becomes higher as shown in
FIG. 4
, the read/precharge operation about the data becomes difficult, thus a data read operation becomes impossible. The reason why the data read operation becomes impossible is that a time loss occurs in the signals Yi and PRC.
Although the local data is read by the signals PRC and Yi and the global data is generated from the data bus sense-amplifier unit
70
, the signals Yi and PRC are disabled after a predetermined time irrespective of a clock frequency, so that the time loss occurs in a precharge operation. In other words, under the condition that a local data bus is not precharged, a previous data and an opposite phase data are not read in the local data bus.
As described above, in the aforementioned prior semiconductor memory device, a local data is read by the signal PRC and the column decoder unit output signal Yi which precharge a local data bus at a high clock frequency, the signals Yi and PRC are disabled after a predetermined time irrespective of a clock frequency. As a result, under the condition that the local data bus is not precharged, a previous data and an opposite phase data are not read in the local data bus.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor memory device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
It is an objective of the present invention to provide a semiconductor memory device which feeds back a signal made by detecting a data sensing when reading a memory chip, precharges a local data bus within a short time, performs a high-speed operation, and enhances a burst characteristic and AC characteristic responsive to the burst characteristic.
To achieve the above objective, in a semiconductor memory device which senses a data signal transmitted from a local data bus during a read operation by using a data bus sense-amplifier unit, and then outputs the data signal to a global data bus, a semiconductor memory device according to a preferred embodiment of the present invention includes: a data bus sense-amplifier output detector unit which is included in the data bus sense-amplifier, performs a logic operation about the data signal sensed by the data bus sense-amplifier unit, and generates a detection signal; and a column precharge control unit for generating a control signal to precharge the local data bus and the data bus sense-amplifier unit according to the detection signal from the data bus sense-amplifier output detector unit.
The data bus sense-amplifier output detector unit includes: a NOR gate for receiving an output signal of the data bus sense-amplifier unit as an input; and an inverter for outputting a control signal to the column precharge control unit according to an output signal of the NOR gate.
The data bus sense-amplifier output detector unit inputs a control signal into a column decoder unit, simultaneously with inputting a control signal into the column precharge control u

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