Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1993-08-19

1994-09-20

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

36518911, 365190, G11C 700

Patent

active

053495578

ABSTRACT:
A semiconductor memory device having an array of memory cells divided into a plurality of blocks including a redundant block, in which each block is treated as a single unit and a faulty block is replaced with the redundant block. Each block has four logic circuits which drives a transistor for pulling up bits lines in a standby state and drives a transistor for pulling up bit lines to prevent data from being lost according to a bit-line pull-up timing signal, a redundant-block enable signal, a block address and a write signal. With this structure, in a faulty block, both of the transistors are always turned off and a supply of currents to the bit lines are cut off. Therefore, even when a block becomes faulty due to a short circuit between the bit lines and the ground potential section, the semiconductor memory device is saved from becoming defective.

REFERENCES:
patent: 4829477 (1989-05-01), Suzuki et al.
patent: 4939693 (1990-07-01), Tran
patent: 4961168 (1990-10-01), Tran
patent: 5274594 (1993-12-01), Yanagisawa et al.

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