Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Differential sensing

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Details

36518901, 36518904, 36518905, 365196, G11C 702

Patent

active

059462531

ABSTRACT:
In a semiconductor memory device in which cell arrays are connected to a shared bus line through sense amplifiers at the time of reading-out and writing operations, a sub-amplifier is provided between two bus lines, the sub-amplifier amplifying a potential difference of reading-out data fetched on the bus lines from the selected sense amplifier and a potential difference of writing data input to the bus lines from the outside. The sub-amplifier has an ability to amplify the potential differences of both of the reading-out data and writing data on the bus lines without separating the bus lines, whereby the amount of delay due to wiring can be reduced.

REFERENCES:
patent: 4511997 (1985-04-01), Nozaki et al.
patent: 5519661 (1996-05-01), Miura
English Translation of Japanese Patent Office Action for Japanese Patent Application 8-181935 dated Dec. 22, 1998.

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