Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1990-06-19

1991-11-26

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

365190, 365203, G11C 700

Patent

active

050688286

ABSTRACT:
A semiconductor memory device having a plurality of memory arrays in which static memory cells are disposed in a lattice arrangement at intersections of word lines and complementary data lines. The load circuits thereof are characterized as having a varying impedance effected by the combination of a first pair of P-channel MOSFETs disposed between the complementary data lines and a first node supplied with a first supply voltage and kept normally in an ON-state, and a pair of transistors, such as a second pair of P-channel MOSFETs, similarly connected as the first pair of P-channel MOSFETs and which are turned off selectively in accordance with a control signal corresponding to a predetermined selection timing signal in a write-in mode. The semiconductor memory device has a plurality of switching circuits which are coupled between the plurality of complementary data lines and a pair of data read and write lines. Each such switching circuit has a first pair of N-channel MOSFETs for selectively coupling the data input circuit of the memory device to a corresponding pair of complementary data lines via the pair of write data lines during a data write-in mode and a pair of P-channel MOSFETs for selectively coupling the corresponding pair of complementary data lines to the data output circuit via the pair of read data lines during the data read-out mode thereof.

REFERENCES:
patent: 4563754 (1986-01-01), Aoyama et al.
patent: 4685086 (1987-08-01), Tran
T. Sakurai et al., "A Low Power 46 ns 256 Kbit CMOS Static Ram with Dynamic Double Word Line," IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, Oct. 1984, pp. 578-584.
S. Miyaoka et al., A 7 ns/350 mW 64K "EZL Compatible RAM", ISSCC 1987, pp. 132-137, DIgest of Technical Papers.

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