Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Bad bit

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Details

36523003, 371 101, G11C 700

Patent

active

053253337

ABSTRACT:
A semiconductor memory device uses a memory cell array having of a plurality of cell array blocks, a redundancy cell array as a replacement for a cell array block containing a faulty memory cell, a replacement-information memory circuit for holding faulty-cell detection information and discrimination information of a cell array block containing a faulty cell in a plurality of memory transistors each, in normal mode, with source and control gate electrodes kept at ground potential and a drain electrode kept at a specified voltage of lower potential than the supply voltage. Each is forced into depletion or enhancement mode depending on the accumulated charge on the floating gate. The memory also includes a redundancy selector for outputting the redundancy signal which goes to active level by the decision based on an information held in this replacement-information memory circuit that a cell array block containing a faulty cell has been selected.

REFERENCES:
patent: 4947378 (1990-08-01), Jinbo et al.
patent: 5018104 (1991-05-01), Urai
patent: 5233566 (1993-08-01), Imamiya et al.

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