Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1983-06-14

1985-08-13

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

365154, G11C 1140

Patent

active

045354260

ABSTRACT:
A memory device of the invention has a P type substrate, a first drain area of N type formed in the substrate, a second drain area of N type formed in the substrate close to the first drain area, and a source area of N.sup.+ type formed around the first and second drain areas so that the source area continuously surrounds the drain areas from three sides, e.g., the right, left and top sides of these areas. The combination of the closed arrangement of the drain areas and the surrounding arrangement of the source area decreases minority carriers generated around the drain areas and prevents unbalanced carrier absorption of the drain areas, thereby suppressing the occurrence of a soft error.

REFERENCES:
patent: 4480319 (1984-10-01), Hotta et al.
Ishihara et al., "A 256K Dynamic MOS RAM with Alpha Immune and Redundancy," ISSCC Dig. Tech. Papers, pp. 74-75, Feb. 10, 1982.
Masuhara et al., "2Kx8b HCMOS Static RAMS," ISSCC Dig. Tech. Papers, pp. 224-225, Feb. 15, 1980.
Yoshimoto et al., pp. 2-217, (preprint), Whole National Meeting of Electronics and Communications Engineers of Japan, "Improvement of a 16K Static MOS RAM Soft Error".

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