Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Including signal comparison

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Details

36518901, 365203, G11C 1300

Patent

active

050954636

ABSTRACT:
A novel semiconductor memory device having address comparator, word line drive circuit sense circuit, and control circuit is disclosed. The comparator judges whether or not a row address read in the present access cycle is in correspondence with that in the last cycle. Where it is judged that the former is not in correspondence with the latter, the control circuit allows the sense circuit to select a word line by this row address to transfer data of a memory cell to the bit line to allow the sense means to sense. On the other hand, where it is judged by the comparator that the former is in correspondence with the latter, since data of the memory cell belonging to the same word line is already sensed in the last cycle, the control circuit allows the readout circuit to read out data from a bit line corresponding to the column address without causing the sense circuit to carry out a sense operation for a second time. Thus, only when the row address changes with respect to that in the last cycle, a sense operation is caused to be carried out. Thus, the readout operation can be performed at a high speed.

REFERENCES:
patent: 4899317 (1990-02-01), Hoekstra et al.

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