Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Bad bit

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3652257, 36523003, G11C 700

Patent

active

053792599

ABSTRACT:
Two redundant blocks RB1 and RB2 are provided independent from the normal memory cell block BL, and selection of the redundant block when redundancy is selected is carried out by a least significant column address signal Y0 and a signal /Y0 complementary thereto in a semiconductor memory device. Therefore, a semiconductor memory device can be provided in which when defective bits exist continuously in a memory cell array, the continuous defective bit can be replaced by two redundant bit lines.

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