Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Bad bit

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Details

36518907, 365204, 36523008, G11C 2900, G11C 700

Patent

active

054425875

ABSTRACT:
In the memory cell provided with spare cells and normal cells, the time required to discriminate the spare column address from the normal column address or vice versa can be reduced, and thereby a high speed memory access can be realized. When an address is given from the counter to a memory circuit having the spare address and the normal address, before the counter outputs an address to the memory circuit, the spare
ormal discriminating circuit acquires previously the address outputted from the counter and discriminates whether the address is the spare address or the normal address. On the basis of this discrimination, the select circuits switch the address to be applied from the select circuits to the memory circuit from the normal address to the spare address or vice versa.

REFERENCES:
patent: 5113371 (1992-05-01), Hamada
patent: 5265055 (1993-11-01), Horiguchi et al.
patent: 5276360 (1994-01-01), Fujima
patent: 5297088 (1994-03-01), Yamaguchi

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