Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Bad bit

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36518907, 36523001, G11C 2900

Patent

active

059782900

ABSTRACT:
A semiconductor memory device comprising a plurality of memory cell arrays including a redundant memory cell for each. Connection between each memory cell array and data input-output terminals can be switched easily by a signal input from the outside in response to a plurality of input-output data widths. Each redundant memory cell compares each bit of an external address input externally with each bit of an internal address of a memory cell having been stored. According to a detection signal from a redundancy judging circuit to detect agreement between both addresses, the memory cell having that address is replaced. This replacement can be carried out not only within the memory cell array having the redundant memory cell but also between different memory cell arrays.

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patent: 5568433 (1996-10-01), Kumar
patent: 5657280 (1997-08-01), Shin et al.
patent: 5666314 (1997-09-01), Akaogi et al.

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