Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1981-07-10

1983-12-06

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Capacitors

365174, 365190, G11C 1124

Patent

active

044197438

ABSTRACT:
Disclosed is a semiconductor memory device in which dynamic cells, each comprising a capacitor and a field effect-type switching transistor, are arrayed at intersecting points of a plurality of bit lines and a plurality of word lines. Either the source electrode or the drain electrode of the transistor is connected to a reference potential line, the other electrode being connected to an electrode of the capacitor. The bit line is commonly connected to the other electrode of the capacitors of a plurality of memory cells arrayed along the bit line. The word line is commonly connected to the gate electrodes of the switching transistors of the plurality of memory cells arrayed along the word line, and the area of the capacitor is greater than the electrode area of a portion where the transistor is connected to the capacitor.

REFERENCES:
patent: 3986180 (1976-10-01), Cade
patent: 4188671 (1980-02-01), Lynes
IBM Technical Disclosure Bulletin, vol. 21, No. 2, Jul. 1978, Anantha et al., "Method of Making 1/N Cell", pp. 601-603.
Selleck et al., "64K Dynamic 1/N Fractional Device Bipolar Memory", 1980 IEEE International Solid-State Circuits Conference, pp. 220-221.
Koyanagi et al., "Novel High Density, Stacked Capacitor MOS RAM", Japanese Journal of Applied Physics, vol. 18, 1979, Supplement 1B-1, pp. 35-42.

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