Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1999-11-22

2000-08-15

Phan, Trong

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, G11C 700

Patent

active

061046493

ABSTRACT:
It is an object of this invention to provide a semiconductor memory device in which a failure can be efficiently remedied even for a larger number of bits. In a multi-bit memory capable of simultaneously exchanging a plurality of data upon reception of an address, square DQ lines (15c) commonly used for each I/O, a spare sense amplifier circuit (13c), a spare column switch (14c), a fuse box (20) for storing the address of a DQ line in which a failure has occurred, and fuse circuits (21-1, 21-2, . . . ) for storing an I/O to which the failure-DQ line belongs are arranged to remedy the failure for each I/O. Since only a memory cell belonging to one I/O where a failure has occurred is replaced, unnecessary replacement is not executed, and the memory cell can be efficiently remedied even for a larger number of bits.

REFERENCES:
patent: 5610865 (1997-03-01), Shin et al.
patent: 5657280 (1997-08-01), Shin et al.
patent: 5699289 (1997-12-01), Takenaka
patent: 5732029 (1998-03-01), Lee et al.
patent: 5732030 (1998-03-01), Dorney
patent: 5740120 (1998-04-01), Okamura
patent: 5970002 (1999-10-01), Yoo

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