Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1996-11-14

1997-12-30

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 371 102, 371 103, G11C 700, G11C 2900

Patent

active

057038171

ABSTRACT:
A plurality of memory cells are arranged at crosspoints between a plurality of word lines and a plurality of bit lines. The memory cells include not only normal cells but also spare cells for saving defects. The saving of the defect is effected by replacing the word line or bit line connected to the normal cell with the word line or bit line connected to the spare cell. The replacement is effected by a corresponding pair of fuse circuit and deciding circuit, that is, the fuse circuit for storing the address of a word line or bit line to be replaced and the deciding circuit for, based on the address, deciding whether or not an accessed word line or bit line be replaced. As such a pair use is made of a plurality of pairs and a plurality of kinds are provided as the word lines or bit lines for replacement and can be used in accordance with the size of defects. It is, therefore, possible to effectively save the defective word line or bit line, while avoiding any uneffective replacement.

REFERENCES:
patent: 5293348 (1994-03-01), Abe
patent: 5392246 (1995-02-01), Akiyama et al.
patent: 5394368 (1995-02-01), Miyamoto
patent: 5475648 (1995-12-01), Fujiwara
patent: 5487039 (1996-01-01), Sukegawa
patent: 5570318 (1996-10-01), Ogawa

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