Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1982-04-22
1984-12-18
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
G11C 700
Patent
active
044894023
ABSTRACT:
A semiconductor memory device provides redundancy using a decoder which examines a memory address and outputs the contents of memory at that address if the decoder determines that the address signal is selecting a correct bit cell in the memory, or clamps the output at a predetermined level if the decoder determines that the address signal is selecting an error bit cell in the memory.
REFERENCES:
patent: 4047163 (1977-09-01), Choate et al.
patent: 4281398 (1981-07-01), McKenny et al.
patent: 4310901 (1982-01-01), Harding et al.
patent: 4365319 (1982-12-01), Takemae
Sakalay, "Correction of Bad Bits in a Memory Matrix", IBM Technical Disclosure Bulletin, vol. 6, No. 10, pp. 1, 2, (Mar. 1964).
Evans et al., "Correction of Memories with Defective Bits", IBM Technical Disclosure Bulletin, vol. 7, No. 6, pp. 436, 437, (Nov. 1964).
Ichinose Kazuaki
Miyamoto Junichi
Saitoh Shinji
Popek Joseph A.
Tokyo Shibaura Denki Kabushiki Kaisha
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