Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Bad bit

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Details

36523003, G11C 700

Patent

active

061377368

ABSTRACT:
The present invention provides a semiconductor memory device having a block selective line selecting circuit connected to a plurality of block selective common lines, each of which is commonly connected to both corresponding normal and redundant memory cell blocks in normal and redundant memory cell arrays, wherein the block selective line selecting circuit is switched into a first state to permit transmissions of decoded normal row address signals having informations of designating a normal row address to which a normal memory cell to be selected belongs when a non-defective normal memory cell is selected in the normal memory cell array, and also the block selective line selecting circuit is switched into a second state to permit transmissions of decoded redundant row address signals having informations of designating a redundant row address to which a redundant memory cell to be selected belongs when a defective normal memory cell is selected in the normal memory cell array.

REFERENCES:
patent: 5576633 (1996-11-01), Rountree et al.

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