Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1994-12-30

1996-09-24

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 36523006, G11C 700, G11C 2900

Patent

active

055597416

ABSTRACT:
In a semiconductor memory device with redundant configuration, a redundant address detection circuit is additionally provided between an I/O buffer and a read/write circuit coupled to a memory cell array. The detection circuit receives both a signal indicating the detection of redundancy from a redundant address setter and a signal instructing a test mode for the memory device, and selectively inverts the logic of data associated with the redundant cell. When the data is supplied to memory cells through the redundant address detection circuit under test mode conditions, only data involved in a redundant address is inverted in logic and is written into a redundant cell. Subsequently, a tester reads out the write data of all memory cells to produce a bit map indicating the address of the inverted data and allowing the tester to detect the address of redundant memory cells.

REFERENCES:
patent: 4592024 (1986-05-01), Sakai et al.
patent: 4866676 (1989-09-01), Crisp et al.
patent: 5091884 (1992-02-01), Kagami

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1934447