Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Data refresh

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Details

36518901, 365233, G11C 700

Patent

active

059011017

ABSTRACT:
In a semiconductor memory device operable in synchronism with a clock signal externally supplied thereto, there are provided a first part which detects a state of a predetermined signal after a given command is input to the semiconductor memory; and a second part which sets, on the basis of the state of the predetermined signal, the semiconductor memory device to a self-refresh mode in which a refresh operation is carried out without an external signal.

REFERENCES:
patent: 5418754 (1995-05-01), Sakakibara
patent: 5469386 (1995-11-01), Obara
patent: 5499213 (1996-03-01), Niimi et al.
patent: 5563837 (1996-10-01), Noguchi
patent: 5583818 (1996-12-01), You et al.
patent: 5629897 (1997-05-01), Iwamoto et al.
patent: 5644544 (1997-07-01), Mizukami

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