Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1997-03-26

1998-12-08

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Differential sensing

365203, 365208, 36523006, G11C 700

Patent

active

058480110

ABSTRACT:
A semiconductor memory device including a memory cell array, bit lines, and sense amplifier groups. The memory cell array is composed of a plurality of memory cells arranged roughly in a matrix pattern. A plurality of the memory cells arranged in a row are activated in response to a row address decode signal. A pair of the bit lines are provided for each column. The data of the corresponding activated memory cells are transmitted to the bit line pair. Each of the sense amplifier groups has n-units of sense amplifiers each connected to the bit line pair, to sense and amplify data read to the bit line pair connected thereto. The respective reference potential terminals of the sense amplifiers of each of the sense amplifier groups are connected to a single common node which can be connected to a reference potential via a sense amplifier activating transistor turned on in response to a row address signal. The sense amplifiers can be operated at high speed, while preventing erroneous operation, because the wiring resistances and the parasitic capacitances of the common source node of the sense amplifiers can be reduced.

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patent: 5640355 (1997-06-01), Muraoka et al.

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