Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing

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365207, G11C 1140

Patent

active

052166341

ABSTRACT:
A semiconductor memory device has pairs of complementary bit lines connected to pairs of complementary data bus lines via transfer elements controlled by column lines. The bit lines are arranged so that mutually adjacent pairs of bit lines are connected to the same pair of data bus lines at a pair of common nodes. The transfer elements for each such mutually adjacent pair of bit lines are controlled by different column lines.

REFERENCES:
patent: 4239993 (1980-12-01), McAlexander, III et al.
patent: 4451906 (1984-05-01), Ikeda
patent: 4476547 (1984-10-01), Miyasaka
patent: 4780852 (1988-10-01), Kajigaya
patent: 4791616 (1988-12-01), Taguchi et al.
patent: 5029330 (1991-07-01), Kajigaya
H. Shimada et al., "A 46-ns 1 Mbit CMOS SRAM", Journal of Solid-State Circuits, vol. 23, No. 1, pp. 53-58 (Feb., 1988).

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