Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1996-02-13

1998-02-17

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Including signal clamping

36518911, 365202, G11C 800

Patent

active

057198110

ABSTRACT:
A load element, which is controlled by a control signal acquired by a logical operation of a write/read enable signal and a row address signal, is provided at a pair of digit lines. This structure provides a semiconductor memory device that suppresses a change in the potential difference between the digit line pair, which is caused by a parasitic resistor, to ensure an uniform read delay time and improve the reading speed.

REFERENCES:
patent: 4903238 (1990-02-01), Miyatake et al.
patent: 5268874 (1993-12-01), Yamauchi
patent: 5392243 (1995-02-01), Nakamura
patent: 5508961 (1996-04-01), Han
IEEE Journal of Solid-State Circuits, vol. 30, No. 6, Jun. 1995, Design of 1.28-GB/s High Bandwidth 2-Mb SRAM for Integrated Memory Array Processor Applications, by Tohru Kimura, Kazuyuki Nakamura, Yoshiharu Aimoto, Takashi Manabe, Nobuyuki Yamashita, Yoshihiro Fujita, Shin'ichiro Okazaki, and Masakazu Yamashina, pp. 637-642.
IEEE Journal of Solid-State Circuits, vol. 29, No. 11, Nov. 1994, A 220-MHz Pipelined 16-Mb BiCMOS SRAM with PLL Proportional Self-Timing Generator, by Kazuyuki Nakamura, Shigeru Kuhara, Tohru Kimura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Toshida and Tohru Yamazaki, pp. 1317-1321.

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1789330