Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Testing

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365210, G11C 700

Patent

active

048021377

ABSTRACT:
A semiconductor memory device includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines, each coupled to the memory cells forming one column, and a MOS transistor connected between a power supply terminal and one end of every bit line. The device further includes at least one test memory cell coupled in series with the MOS transistor, thus forming a series circuit connected between the power supply terminal and the ground.

REFERENCES:
patent: 4506350 (1985-03-01), Asano et al.
patent: 4597062 (1986-06-01), Asano et al.
patent: 4651304 (1987-03-01), Takata
patent: 4692901 (1987-09-01), Kumanoya et al.
Japanese Patent Disclosure (Kokai) No. 57-105891, M. Yoshida, Jul. 1, 1982.
Japanese Patent Disclosure (Kokai) No. 57-172598, M. Asano, Oct. 23, 1982.

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