Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1992-06-25
1993-11-02
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Bad bit
3652257, 36523006, G11C 800
Patent
active
052589536
ABSTRACT:
In a redundant memory device, the redundant memory device is provided which is characterized in that the supply of a driving pulse to a comparison and selection device which generates an activating pulse of a reserve row/column in response to the result of comparison of the address of a defective memory cell and an input address code can be programmed so as to be inhibited for a surplus comparison and selection device during the inspection process. By this arrangement, the power consumption in the comparison and selection device can be reduced, and high level of integration of the memory chip can be facilitated accordingly.
REFERENCES:
patent: 4586170 (1986-04-01), O'Toole et al.
patent: 4587639 (1986-05-01), Aoyama et al.
patent: 4723227 (1988-02-01), Murotani
patent: 4951253 (1990-08-01), Sahara et al.
LaRoche Eugene R.
NEC Corporation
Yoo D. Hyun
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