Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1987-11-18

1989-01-31

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

For complementary information

365156, 365177, 365 94, G11C 700, G11C 1100, G11C 1134, G11C 1700

Patent

active

048021261

ABSTRACT:
For preventing a semiconductor substrate from undesirable discharging of electric charges, there is disclosed a semiconductor memory device fabricated on the semiconductor substrate and having a read-out mode and a write-in mode, comprising: (a) a plurality of memory cells arranged in rows and columns and having read only memory cells and random access memory cells; (b) a plurality of word lines each operative to activate the memory cells of each row in the read-out mode and the write-in mode; (c) a plurality of first data lines each operative to propagate a voltage level; (d) a plurality of second data lines each paired with each of the first data lines to form a data line pair coupled to the memory cells of each column, each of the second data lines being operative to propagate the complementary voltage level of the voltage level on the first data line, the voltage level and the complementary voltage level representing a bit of data information; and (d) a plurality of read-write buffer circuits each coupled to each of the data line pair so as to transfer the bit of data information thereto, wherein each of the read only memory cells comprises a series combination of two transistors capable of providing a conduction path between one of the first and second data lines and a source of voltage in the read-out mode, at least one of the two transistors being operative to block the conduction path in the write-in mode.

REFERENCES:
patent: 4606010 (1986-08-01), Saito
patent: 4665505 (1987-05-01), Miyakawa et al.
patent: 4713796 (1987-12-01), Ogiue et al.

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